- 14 Jan, 2021 4 commits
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Jani Nikula authored
Start following the usual naming pattern for functions. No functional changes. Reviewed-by:
Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/e37623750c592c08720f3b340cf85862d0f0ca12.1610127741.git.jani.nikula@intel.com
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Jani Nikula authored
In a long overdue refactoring, split out all panel sequencer code from intel_dp.c to new intel_pps.[ch]. The first part is mostly just code movement as-is, without cleanups or functional changes. We need to add a vlv_get_dpll() helper to get at the vlv/chv dpll from pps code. v2: Rebase. Reviewed-by:
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Jani Nikula authored
Always prefer the kernel types over stdint types in i915. Cc: Imre Deak <imre.deak@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
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Jani Nikula authored
skl_scaler_get_filter_select() isn't static and can't be inline. Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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- 13 Jan, 2021 21 commits
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Imre Deak authored
The DP PHY vswing/pre-emphasis level programming the driver does is related to the DPTX -> first LTTPR link segment only. Accordingly it should be only programmed when link training the first LTTPR and kept as-is when training subsequent LTTPRs and the DPRX. For these latter PHYs the vs/pe levels will be set in response to writing the DP_TRAINING_LANEx_SET_PHY_REPEATERy DPCD registers (by an upstream LTTPR TX PHY snooping this write access of its downstream LTTPR/DPRX RX PHY). The above is also described in DP Standard v2.0 under 3.6.6.1. While at it simplify and add the LTTPR that is link trained to the debug message in intel_dp_set_signal_levels(). Fixes: b30edfd8 ("drm/i915: Switch to LTTPR non-transparent mode link training") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
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Imre Deak authored
intel_dp_set_signal_levels() is needed for link training, so move it to intel_dp_link_training.c. Signed-off-by:
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Anshuman Gupta authored
Enable HDCP 2.2 MST support till Gen12. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
Ramalingam C <ramalingam.c@intel.com> Tested-by:
Karthik B S <karthik.b.s@intel.com> Signed-off-by:
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Anshuman Gupta authored
Authenticate and enable port encryption only once for an active HDCP 2.2 session, once port is authenticated and encrypted enable encryption for each stream that requires encryption on this port. Similarly disable the stream encryption for each encrypted stream, once all encrypted stream encryption is disabled, disable the port HDCP encryption and deauthenticate the port. v2: - Add connector details in drm_err. [Ram] - 's/port_auth/hdcp_auth_status'. [Ram] - Added a debug print for stream enc. v3: - uniformity for connector detail in DMESG. [Ram] Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Reviewed-by:
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Anshuman Gupta authored
Add support for HDCP 2.2 DP MST shim callback. This adds existing DP HDCP shim callback for Link Authentication and Encryption and HDCP 2.2 stream encryption callback. v2: - Added a WARN_ON() instead of drm_err. [Uma] - Cosmetic changes. [Uma] v3: - 's/port_data/hdcp_port_data' [Ram] - skip redundant link check. [Ram] v4: - use pipe instead of port to access HDCP2_STREAM_STATUS Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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Anshuman Gupta authored
Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS and HDCP2_AUTH_STREAM register in i915_reg header. B.Spec: 21780 B.Spec: 14410 B.Spec: 50573 v2 - Modified naming convention of HDCP2_STREAM_STATUS for pre-gen12 platforms inline with B.Spec. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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Anshuman Gupta authored
This requires for HDCP 2.2 MST check link. As for DP/HDMI shims check_2_2_link retrieves the connector from dig_port, this is not sufficient or DP MST connector, there can be multiple DP MST topology connector associated with same dig_port. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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Anshuman Gupta authored
Add support for multiple mst stream in hdcp port data which will be used by RepeaterAuthStreamManage msg and HDCP 2.2 security f/w for m' validation. Security f/w doesn't have any provision to mark the stream_type for each stream separately, it just take single input of stream_type while authenticating the port and applies the same stream_type to all streams. So driver mark each stream_type with common highest supported content type for all streams in DP MST Topology. Security f/w supports RepeaterAuthStreamManage msg and m' validation only once during port authentication and encryption. Though it is not compulsory, security fw should support dynamic update of content_type and should support RepeaterAuthStreamManage msg and m' validation whenever required. v2: - Init the hdcp port data k for HDMI/DP SST stream. v3: - Cosmetic changes. [Uma] v4: - 's/port_auth/hdcp_port_auth'. [Ram] - Commit log improvement. v5: - Comment and commit log improvement. [Ram] v6: - Check first connector connected status before intel_encoder_is_mst to avoid any NULL pointer dereference. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
Juston Li <juston.li@intel.com> Acked-by:
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Anshuman Gupta authored
Let's define Maximum MST content streams up to four generically which can be supported by modern display controllers. Cc: Sean Paul <seanpaul@chromium.org> Cc: Ramalingam C <ramalingam.c@intel.com> Acked-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by:
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Anshuman Gupta authored
Fix the size of WIRED_REPEATER_AUTH_STREAM_REQ cmd buffer size. It is based upon the actual number of MST streams and size of wired_cmd_repeater_auth_stream_req_in. Excluding the size of hdcp_cmd_header. v2: - hdcp_cmd_header size annotation nitpick. [Tomas] Cc: Tomas Winkler <tomas.winkler@intel.com> Cc: Ramalingam C <ramalingam.c@intel.com> Acked-by:
Tomas Winkler <tomas.winkler@intel.com> Reviewed-by:
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Anshuman Gupta authored
hdcp_port_data is specific to a port on which HDCP encryption is getting enabled, so encapsulate it to intel_digital_port. This will be required to enable HDCP 2.2 stream encryption. v2: - 's/port_data/hdcp_port_data'. [Ram] Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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Anshuman Gupta authored
Pass dig_port as an argument to intel_hdcp_init() and intel_hdcp2_init(). This will be required for HDCP 2.2 stream encryption. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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Anshuman Gupta authored
Enable HDCP 1.4 over DP MST for Gen12. v2: - Enable HDCP for <= Gen12 platforms. [Ram] v3: - Connector detials in debug msg. [Ram] Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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Anshuman Gupta authored
Enable HDCP 1.4 DP MST stream encryption. Enable stream encryption once encryption is enabled on the DP transport driving the link for each stream which has requested encryption. Disable stream encryption for each stream that no longer requires encryption before disabling HDCP encryption on the link. v2: - Added debug print for stream encryption. - Disable the hdcp on port after disabling last stream encryption. v3: - Cosmetic change, removed the value less comment. [Uma] v4: - Split the Gen12 HDCP enablement patch. [Ram] - Add connector details in drm_err. v5: - uniformity for connector detail in DMESG. [Ram] - comments improvement. [Ram] Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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Anshuman Gupta authored
Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP encryption over DP MST Transport Link. HDCP 1.4 stream encryption requires to validate the stream encryption status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link in order to enable/disable the stream encryption. Both of above requirement are same for all Gen with respect to B.Spec Documentation. v2: - Cosmetic changes function name, error msg print and stream typo fixes. [Uma] v3: - uniformity for connector detail in DMESG. [Ram] Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: -
Anshuman Gupta authored
DP MST stream encryption status requires time of a link frame in order to change its status, but as there were some HDCP encryption timeout observed earlier, it is safer to use ENCRYPT_STATUS_CHANGE_TIMEOUT_MS timeout for stream status too, it requires to move the macro to a header. It will be used by both HDCP{1.x,2.x} stream status timeout. Related: 'commit 7e90e8d0 ("drm/i915: Increase timeout for Encrypt status change")' Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: -
Anshuman Gupta authored
Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine instances lies in Transcoder instead of DDI as in Gen11. This requires hdcp driver to use mst_master_transcoder for link authentication and stream transcoder for stream encryption separately. This will be used for both HDCP 1.4 and HDCP 2.2 over DP MST on Gen12. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: -
Anshuman Gupta authored
There can be situation when DP MST connector is created without mst modeset being done, in those cases connector->encoder will be NULL. MST connector->encoder initializes after modeset. Don't enable HDCP in such cases to prevent any crash. Cc: Ramalingam C <ramalingam.c@intel.com> Cc: Juston Li <juston.li@intel.com> Tested-by:
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Anshuman Gupta authored
Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0 It requires to call intel_hdcp_handle_cp_irq() in case of CP_IRQ is triggered by a sink in DP-MST topology. Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com> Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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Anshuman Gupta authored
Get DRM connector reference count while scheduling a prop work to avoid any possible destroy of DRM connector when it is in DRM_CONNECTOR_REGISTERED state. Fixes: a6597faa ("drm/i915: Protect workers against disappearing connectors") Cc: Sean Paul <seanpaul@chromium.org> Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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Anshuman Gupta authored
When crtc state need_modeset is true it is not necessary it is going to be a real modeset, it can turns to be a fastset instead of modeset. This turns content protection property to be DESIRED and hdcp update_pipe left with property to be in DESIRED state but actual hdcp->value was ENABLED. This issue is caught with DP MST setup, where we have multiple connector in same DP_MST topology. When disabling HDCP on one of DP MST connector leads to set the crtc state need_modeset to true for all other crtc driving the other DP-MST topology connectors. This turns up other DP MST connectors CP property to be DESIRED despite the actual hdcp->value is ENABLED. Above scenario fails the DP MST HDCP IGT test, disabling HDCP on one MST stream should not cause to disable HDCP on another MST stream on same DP MST topology. v2: - Fixed connector->base.registration_state == DRM_CONNECTOR_REGISTERED WARN_ON. v3: - Commit log improvement. [Uma] - Added a comment before scheduling prop_work. [Uma] Fixes: 33f9a623 ("drm/i915/hdcp: Update CP as per the kernel internal state") Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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- 12 Jan, 2021 1 commit
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Matt Roper authored
DG1's vswing tables are the same for eDP and HDMI but have slight differences from ICL/TGL for DP. v2: - Use a "_hbr2_hbr3" suffix on the table name to make it more clear that the same table is used for both HBR2 and HBR3 link rates. (Swathi) Bspec: 49291 Cc: Clinton Taylor <Clinton.A.Taylor@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210108222528.1954514-1-matthew.d.roper@intel.comReviewed-by:
Clint Taylor <Clinton.A.Taylor@intel.com>
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- 11 Jan, 2021 4 commits
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Ville Syrjälä authored
Some new eDP panels don't like to operate at the max parameters, and instead we need to go for an optimal confiugration. That unfortunately doesn't work with older eDP panels which are generally only guaranteed to work at the max parameters. To solve these two conflicting requirements let's start with the optimal setup, and if that fails we start again with the max parameters. The downside is probably an extra modeset when we switch strategies but I don't see a good way to avoid that. For a bit of history we first tried to go for the fast+narrow in commit 7769db58 ("drm/i915/dp: optimize eDP 1.4+ link config fast and narrow"). but that had to be reverted due to regression on older panels in commit f11cb1c1 ("drm/i915/dp: revert back to max link rate and lane count on eDP"). So now we try to get the best of both worlds by using both strategies. v2: Deal with output_bpp and uapi vs. hw state split Reword some comments v3: Rebase Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Albert Astals Cid <aacid@kde.org> # v5.0 backport Cc: Emanuele Panigati <ilpanich@gmail.com> # v5.0 backport Cc: Matteo Iervasi <matteoiervasi@gmail.com> # v5.0 backport Cc: Timo Aaltonen <tjaalton@ubuntu.com> Cc: Kai-Heng Feng <kai.heng.feng@canonical.com> Reviewed-by:
Manasi Navare <manasi.d.navare@intel.com> References: https://bugs.freedesktop.org/show_bug.cgi?id=105267 References: https://bugs.freedesktop.org/show_bug.cgi?id=109959 References: https://gitlab.freedesktop.org/drm/intel/issues/272Signed-off-by:
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Ville Syrjälä authored
Eliminate checkpatch warnings from intel_cursor.c: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: Possible repeated word: 'by' Signed-off-by:
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José Roberto de Souza authored
There was some misinterpretation of specification, when DDIX_USED is set, the next bit means 0 for DP and 1 for HDMI. Anyways this misinterpretation is not causing any issues, this change is just to comply with specification. Also as for us it do not matters if it is HDMI or DP, not checking the port type that HTI is using. Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Jani Nikula authored
The pch_get_backlight(), lpt_get_backlight(), and lpt_set_backlight() functions operate directly on the hardware registers. If inverting the value is needed, using intel_panel_compute_brightness(), it should only be done in the interface between hardware registers and panel->backlight.level. The CPU mode takeover code added in commit 5b1ec9ac ("drm/i915/backlight: Fix backlight takeover on LPT, v3.") reads the hardware register and converts to panel->backlight.level correctly, however the value written back should remain in the hardware register "domain". This hasn't been an issue, because GM45 machines are the only known users of i915.invert_brightness and the brightness invert quirk, and without one of them no conversion is made. It's likely nobody's ever hit the problem. Fixes: 5b1ec9ac ("drm/i915/backlight: Fix backlight takeover on LPT, v3.") Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lyude Paul <lyude@redhat.com> Cc: <stable@vger.kernel.org> # v5.1+ Reviewed-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
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- 08 Jan, 2021 3 commits
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Chris Wilson authored
As with the regular suspend paths, also disable the wakeref assertions as we disable the driver during shutdown. Reported-by:
Hans de Goede <hdegoede@redhat.com> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2899 Fixes: fe0f1e3b ("drm/i915: Shut down displays gracefully on reboot") Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Hans de Goede <hdegoede@redhat.com> Tested-by:
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Anshuman Gupta authored
We need a power_domain wakeref in pps_{lock,unlock} to prevent a race while resetting pps state in intel_power_sequencer_reset(). intel_power_sequencer_reset() need a pps_mutex to access pps_pipe but it can't grab pps_mutex due to deadlock with power_well functions are called while holding pps_mutex. intel_power_sequencer_reset() is called by power_well function associated with legacy platforms like vlv and chv therefore re-use the POWER_DOMAIN_DISPLAY_CORE power domain, which only used by vlv and chv display power domain. This will avoids the unnecessary noise of unrelated power wells in pps_{lock,unlock}. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: -
Rodrigo Vivi authored
sync-up to not fall too much behind. Signed-off-by:Rodrigo Vivi <rodrigo.vivi@intel.com>
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- 07 Jan, 2021 7 commits
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git://anongit.freedesktop.org/drm/drm-miscDaniel Vetter authored
drm-misc-next for v5.12: Core Changes: - Lots of drm documentation updates by Simor Ser. - Require that each crtc has a unique primary plane. - Add fixme that fbdev_generic_setup is confusing. Driver Changes: - Update addresses for TI display drivers maintainers. - Make DRM_VIRTIO_GPU select VIRTIO. - Small fixes to qxl, virtio, hisilicon, tve200, panel/s6e63m0. Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/fdfbfd7a-b91d-3f59-11c8-984704ce0ee1@linux.intel.com
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git://linuxtv.org/pinchartl/mediaDaniel Vetter authored
- Add default modes for connectors in unknown state - R-Car DU conversion to DRM-managed API - R-Car DU miscellaneous fixes - Miscellaneous bridge and bridge bindings fixes - Assorted misc driver cleanups - Constify drm_driver for PCI devices Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-intelDaniel Vetter authored
- Display hotplug fix for gen2/gen3 (Chris) - Remove trailing semicolon (Tom) - Suppress display warnings for old ifwi presend on our CI (Chris) - OA/Perf related workaround (Lionel) - Replace I915_READ/WRITE per new uncore and display read/write functions (Jani) - PSR improvements (Jose) - HDR and other color changes on LSPCON (Uma, Ville) - FBC fixes for TGL (Uma) - Record plane update times for debugging (Chris) - Refactor panel backlight control functions (Dave) - Display power improvements (Imre) - Add VRR register definition (Manasi) - Atomic modeset improvements for bigjoiner pipes (Ville) - Switch off the scanout during driver unregister (Chris) - Clean-up DP's FEW enable (Manasi) - Fix VDSCP slice count (Manasi) - Fix and clean up around rc_model_size for DSC (Jani) - Remove Type-C noisy debug warn message (Sean) - Display HPD code clean-up (Ville) - Refactor Intel Display (Dave) - Start adding support for Intel's eDP backlight controls (Lyude) Signed-off-by:
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Hans de Goede authored
drm/i915/dsi: Use unconditional msleep for the panel_on_delay when there is no reset-deassert MIPI-sequence Commit 25b4620e ("drm/i915/dsi: Skip delays for v3 VBTs in vid-mode") added an intel_dsi_msleep() helper which skips sleeping if the MIPI-sequences have a version of 3 or newer and the panel is in vid-mode; and it moved a bunch of msleep-s over to this new helper. This was based on my reading of the big comment around line 730 which starts with "Panel enable/disable sequences from the VBT spec.", where the "v3 video mode seq" column does not have any wait t# entries. Given that this code has been used on a lot of different devices without issues until now, it seems that my interpretation of the spec here is mostly correct. But now I have encountered one device, an Acer Aspire Switch 10 E SW3-016, where the panel will not light up unless we do actually honor the panel_on_delay after exexuting the MIPI_SEQ_PANEL_ON sequence. What seems to set this model apart is that it is lacking a MIPI_SEQ_DEASSERT_RESET sequence, which is where the power-on delay usually happens. Fix the panel not lighting up on this model by using an unconditional msleep(panel_on_delay) instead of intel_dsi_msleep() when there is no MIPI_SEQ_DEASSERT_RESET sequence. Fixes: 25b4620e ("drm/i915/dsi: Skip delays for v3 VBTs in vid-mode") Signed-off-by:
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git://git.pengutronix.de/git/pza/linuxDaniel Vetter authored
drm/imx: fixes and drm managed resources - Reduce stack usage in ipu-di. - Fix imx-ldb for compile tests. - Make drm encoder control functions optional. - Add drm managed variants drmm_encoder_alloc(), drmm_simple_encoder_alloc(), drmm_universal_plane_alloc(), and drmm_crtc_alloc_with_planes() for drm_encoder_init(), drm_simple_encoder_init(), drm_universal_plane_init(), and drm_crtc_init_with_planes(), respectively. - Update imx-drm to use the new functions for drm managed resource allocation, moving initialization from bind to probe where possible. - Fix imx-tve clock provider leak. Signed-off-by:
Daniel Vetter <daniel.vetter@intel.com> [danvet: Fix conflict between doc changes by both Philipp and Simon Ser, see 9999587b ("drm: rework description of primary and cursor planes")] From: Philipp Zabel <p.zabel@pengutronix.de> Link: https://patchwork.freedesktop.org/patch/msgid/c745fc1596898932c9454fd2979297b4242566a2.camel@pengutronix.de
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Daniel Vetter authored
Merge tag 'topic/dp-hdmi-2.1-pcon-2020-12-23' of git://anongit.freedesktop.org/drm/drm-intel into drm-next Add support for DP-HDMI2.1 PCON From the series cover letter: This patch series attempts to add support for a DP-HDMI2.1 Protocol Convertor. The VESA spec for the HDMI2.1 PCON are proposed in Errata E5 to DisplayPort_v2.0: https://vesa.org/join-vesamemberships/member-downloads/?action=stamp&fileid=42299 The details are mentioned in: VESA DP-to-HDMI PCON Specification Standalone Document https://groups.vesa.org/wg/DP/document/15651 This series starts with adding support for FRL (Fixed Rate Link) Training between the PCON and HDMI2.1 sink. As per HDMI2.1 specification, a new data-channel or lane is added in FRL mode, by repurposing the TMDS clock Channel. Through FRL, higher bit-rate can be supported, ie. up to 12 Gbps/lane (48 Gbps over 4 lanes). With these patches, the HDMI2.1 PCON can be configured to achieve FRL training based on the maximum FRL rate supported by the panel, source and the PCON. The approach is to add the support for FRL training between PCON and HDMI2.1 sink and gradually add other blocks for supporting higher resolutions and other HDMI2.1 features, that can be supported by pcon for the sources that do not natively support HDMI2.1. This is done before the DP Link training between the source and PCON is started. In case of FRL training is not achieved, the PCON will work in the regular TMDS mode, without HDMI2.1 feature support. Any interruption in FRL training between the PCON and HDMI2.1 sink is notified through IRQ_HPD. On receiving the IRQ_HPD the concerned DPCD registers are read and FRL training is re-attempted. Currently, we have tested the FRL training and are able to enable 4K display with TGL Platform + Realtek PCON RTD2173 with HDMI2.1 supporting panel. Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-miscDaniel Vetter authored
drm-misc-next for v5.12: UAPI Changes: - Not necessarily one, but we document that userspace needs to force probe connectors. Cross-subsystem Changes: - Require FB_ATY_CT for aty on sparc64. - video: Fix documentation, and a few compiler warnings. - Add devicetree bindings for DP connectors. - dma-buf: Update kernel-doc, and add might_lock for resv objects in begin/end_cpu_access. Core Changes: - ttm: Warn when releasing a pinned bo. - ttm: Cleanup bo size handling. - cma-helper: Remove prime infix, and implement mmap as GEM CMA functions. - Split drm_prime_sg_to_page_addr_arrays into 2 functions. - Add a new api to install irq using devm. - Update panel kerneldoc to inline style. - Add DP support to drm/bridge. - Assorted small fixes to ttm, fb-helper, scheduler. - Add atomic_commit_setup function callback. - Automatically use the atomic gamma_set, instead of forcing drivers to declare the default atomic version. - Allow using degamma for legacy gamma if gamma is not available. - Clarify that primary/cursor planes are not tied to 1 crtc (depending on possible_crtcs). - ttm: Cleanup the lru handler. Driver Changes: - Add pm support to ingenic. - Assorted small fixes in radeon, via, rockchip, omap2fb, kmb, gma500, nouveau, virtio, hisilicon, ingenic, s6e63m0 panel, ast, udlfb. - Add BOE NV110WTM-N61, ys57pss36bh5gq, Khadas TS050 panels. - Stop using pages with drm_prime_sg_to_page_addr_arrays, and switch all callers to use ttm_sg_tt_init. - Cleanup compiler and docbook warnings in a lot of fbdev devices. - Use the drmm_vram_helper in hisilicon. - Add support for BCM2711 DSI1 in vc4. - Add support for 8-bit delta RGB panels to ingenic. - Add documentation on how to test vkms. - Convert vc4 to atomic helpers. - Use degamma instead of gamma table in omap, to add support for CTM and color encoding/range properties. - Rework omap DSI code, and merge all omapdrm modules now that the last omap panel is now a drm panel. - More refactoring of omap dsi code. - Enable 10/12 bpc outputs in vc4. Signed-off-by:
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