- 19 Feb, 2018 40 commits
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Matthias Kaehlcke authored
The double parentheses are not needed. Removing them fixes the following warning when building with clang: drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c:419:29: error: equality comparison with extraneous parentheses [-Werror,-Wparentheses-equality] if ((data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2)) { Reviewed-by:Guenter Roeck <groeck@chromium.org> Signed-off-by:
Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Matthias Kaehlcke authored
In several locations the driver uses AMD_CG_STATE_UNGATE (type enum amd_clockgating_state) instead of AMD_PG_STATE_UNGATE (type enum amd_powergating_stat) and vice versa. Both constants have the same value, so this doesn't cause any problems, but we still want to pass the correct type. Fixing the mismatch resolves multiple warnings like this when building with clang: drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:169:7: error: implicit conversion from enumeration type 'enum amd_powergating_state' to different enumeration type 'enum amd_clockgating_state' [-Werror,-Wenum-conversion] AMD_PG_STATE_UNGATE); Reviewed-by: -
Eric Huang authored
PSP will disable legacy mmhub PG setting that is programming registers, and drive will use SMC message to set it up. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
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Eric Huang authored
new generic interface is added in powerplay. Signed-off-by:
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Eric Huang authored
mmhub PG is enabled by SMU FW only for Raven. Signed-off-by:
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Eric Huang authored
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Dan Carpenter authored
We deleted some code in e154162e ("drm/amd/powerplay: refine pp code for raven") but there were a few related bits that were missed. Let's delete them as well. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Tom St Denis authored
Since 12 of the 16 bytes are not initialized with anything let's ensure they're sensibly zeroed out otherwise debugfs callers will read back garbage (because they assume debugfs wrote sensible data back...) Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Charlene Liu authored
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Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Tony Cheng authored
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Krunoslav Kovac authored
There are several optimizations: 1) Use predefined SRGB, don't calculate. This is the most common case. 2) Precompute HW X points at boot since they're fixed in ColModule 3) Precompute PQ - it never changes and is very CPU intensive in fixed pt. 4) Reduce number of points in ColModule to 512 (32x16) from 1024. This also requires reducing some regions for legacy DCEs to 16 pts at most. Performance 1) is super-fast, build_output_tf is 1-2us, down from 25000-30000. Programming also fast since only one reg write. 2)+3) gives build_output_tf for PQ in ~100us range, down from ~80000-110000 2) + 4) results in slightly over 50% improvement. It gives an idea of the savings when we can't use SRGB or PQ table (e.g. sdr white level > 80). There's also a bit of refactoring: renaming some stuff that was misleading and removing a lot of magic numbers that novices might not be able to understand where they come from and what they mean. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Charlene Liu authored
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Charlene Liu authored
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Tony Cheng authored
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John Barberiz authored
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John Barberiz <jbarberi@amd.com> Reviewed-by:
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Yongqiang Sun authored
System soft hang when hotplug specific 4K DP panel due to link caps read error and incorrect link setting parmas to enable dp. Add status check for DPCD read and add return value for detect dp, in case of false, return from caller, avoid further false operation. Signed-off-by:
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Roman Li authored
Fixing null-deref on Vega10 due to regression after 'fix cursor related Pstate hang' change. Added null checks in setting cursor position. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Reviewed-by:
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Nikola Cornij authored
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Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
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Eric Yang authored
As a precaution to prevent cases where cursor is enabled on a pipe that is disabled, always turn off cursor when disconnecting plane. Signed-off-by:
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Eric Bernstein authored
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Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Ken Chalmers authored
* Previous code did some calculations with a mix of normal integers and integers aligned as U2.24 fixed-point values. * There were bugs in the conversion of the final result into the S4.19 values required for the registers. Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
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Eric Yang authored
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Eric Yang authored
Move cursor programming to inside the OTG_MASTER_UPDATE_LOCK If graphics plane go from 1 pipe to hsplit, the cursor updates after mpc programming and unlock. Which means there is a window of time where cursor is enabled on the wrong pipe if it's on the right side of the screen (i.e. case where cursor need to move from pipe 0 to pipe 3 post split). This will cause pstate hang. Solution is to program the cursor while still locked. Signed-off-by:
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Mikita Lipski authored
Because AMDGPU_CRTC_IRQ_VLINE1 = 6, it expected 6 more crtcs to be programed with disabled irq state in amdgpu_irq_disable_all. That caused errors and accessed the wrong memory location. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Yongqiang Sun authored
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Yongqiang Sun authored
When disable plane, check power gate flag in hubp with pipe_ctx, not with res_pool. Signed-off-by:
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Christian König authored
Otherwise we might overwrite stuff which is still in use. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Tony Cheng authored
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John Barberiz authored
If non-standard gamma type detected set identity matrix flag so that we can bypass the gamma mode. Signed-off-by:
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Charlene Liu authored
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Leo (Sunpeng) Li authored
If CONFIG_DEBUG_FS is disabled, then CRC should also be disabled. Therefore, amdgpu_dm_crtc_handle_crc_irq was redefined as a no-op function within amdgpu_dm.h. However, since amdgpu_dm.h is included in multiple files, this caused conflicts when linking during compile. Therefore, Use a macro to define the function as a no-op instead. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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Jerry (Fangzhi) Zuo authored
There is no need to call drm_mode_set_crtcinfo() again once crtc timing is decided. Otherwise non-native/unsupported timing might get overwritten. Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Martin Tsai authored
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Martin Tsai <martin.tsai@amd.com> Reviewed-by:
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Charlene Liu authored
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Harry Wentland authored
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Christian König authored
It also needs to be initialized. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Christian König authored
Without it we run into a memory leak. Signed-off-by:
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Alex Deucher authored
No longer used since we changed the MC programming sequence. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Alex Deucher authored
Using the wrong mask. Reviewed-by:
Hans de Ruiter <hans@keasigmadelta.com> Signed-off-by:
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