The sibling cpu bringup is extremely fragile.  We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.

This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.

In order to achieve this:

1) Change sun4v_init_mondo_queues() so that it can operate in
   several modes.

   It can allocate the queues, or install them in the current
   processor, or both.

   The boot cpu does both in it's call early on.

   Later, the boot cpu allocates the sibling cpu queue, starts
   the sibling cpu, then the sibling cpu loads them in.

2) init_cur_cpu_trap() is changed to take the current_thread_info()
   as an argument instead of reading %g6 directly on the current
   cpu.

3) Create a trampoline stack for the sibling cpus.  We do our basic
   kernel calls using this stack, which is locked into the kernel
   image, then go to our proper thread stack after taking over the
   trap table.

4) While we are in this delicate startup state, we put 0xdeadbeef
   into %g4/%g5/%g6 in order to catch accidental accesses.

5) On the final prom_set_trap_table*() call, we put &init_thread_union
   into %g6.  This is a hack to make prom_world(0) work.  All that
   wants to do is restore the %asi register using
   get_thread_current_ds().

Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else.  This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>

For 32 cpus and a slow console, it just wedges the
machine especially with DETECT_SOFTLOCKUP enabled.
Signed-off-by: David S. Miller <davem@davemloft.net>

The whole algorithm was wrong.  What we need to do is:

1) Walk each PCI bus above this device on the path to the
   PCI controller nexus, and for each:
      a) If interrupt-map exists, apply it, record IRQ controller node
      b) Else, swivel interrupt number using PCI_SLOT(), use PCI bus
	 parent OBP node as controller node
      c) Walk up to "controller node" until we hit the first PCI bus
	 in this domain, or "controller node" is the PCI controller
	 OBP node
2) If we walked to PCI controller OBP node, we're done.
3) Else, apply PCI controller interrupt-map to interrupt.

There is some stuff that needs to be checked out for ebus and
isa, but the PCI part is good to go.
Signed-off-by: David S. Miller <davem@davemloft.net>

We'll lose events that way.
Signed-off-by: David S. Miller <davem@davemloft.net>

We need to set the global register set _AND_ disable
PSTATE_IE in %pstate.  The original patch sequence was
leaving PSTATE_IE enabled when returning to kernel mode,
oops.

This fixes the random register corruption being seen
on SUN4V.
Signed-off-by: David S. Miller <davem@davemloft.net>

So we can read the %gl register for debugging.
Signed-off-by: David S. Miller <davem@davemloft.net>

So that free_irq() disable's the IRQ correctly.
Signed-off-by: David S. Miller <davem@davemloft.net>

Call it from register_one_mondo().
Signed-off-by: David S. Miller <davem@davemloft.net>

They are bogus and haven't been referenced in years.
Signed-off-by: David S. Miller <davem@davemloft.net>

Signed-off-by: David S. Miller <davem@davemloft.net>

The C function is named sun4v_do_mna not sun4v_mna.
Signed-off-by: David S. Miller <davem@davemloft.net>

No trap levels above 2 in privileged mode on SUN4V.
Signed-off-by: David S. Miller <davem@davemloft.net>

By calling uart_handle_break().  We'll still do the
"sun_do_break()" handling if the user gives two
breaks in a row.

We should probably do this in the other Sparc serial
drivers too.
Signed-off-by: David S. Miller <davem@davemloft.net>

Forgot to multiply by 8 * 1024, oops.  Correct the size constant when
the virtual-dma arena is 2GB in size, it should bet 256 not 128.

Finally, log some info about the TSB at probe time.
Signed-off-by: David S. Miller <davem@davemloft.net>

Until the uart is openned, port->info is NULL.

Also, init the port->irq properly and give a non-zero
port->membase so that the uart device reporting is done.
Signed-off-by: David S. Miller <davem@davemloft.net>

Need to use ASI_QUAD_LDD_PHYS_4V instead.
Signed-off-by: David S. Miller <davem@davemloft.net>

For SUN4V, we were clobbering %o5 to do the hypervisor call.
This clobbers the saved %pstate value and we end up writing
garbage into that register as a result.  Oops.
Signed-off-by: David S. Miller <davem@davemloft.net>

Needs to use physical addressing just like cheetah_plus.
Signed-off-by: David S. Miller <davem@davemloft.net>

Signed-off-by: David S. Miller <davem@davemloft.net>

Need to translate through the interrupt-map{,-mask] properties.
Signed-off-by: David S. Miller <davem@davemloft.net>

Use prom_startcpu_cpuid() on SUN4V instead of prom_startcpu().

We should really test for "SUNW,start-cpu-by-cpuid" presence
and use it if present even on SUN4U.
Signed-off-by: David S. Miller <davem@davemloft.net>

When crawling up the PCI bus chain, stop at the first node
that has an interrupt-map property before we hit the root.

Also, if we use a bus interrupt-{map,mask} do not forget to
update the 'intmask' pointer as we do for the 'intmap' pointer.
Signed-off-by: David S. Miller <davem@davemloft.net>

On SUN4V, force IRQ state to idle in enable_irq().  However,
I'm still not sure this is %100 correct.

Call add_interrupt_randomness() on SUN4V too.
Signed-off-by: David S. Miller <davem@davemloft.net>

Signed-off-by: David S. Miller <davem@davemloft.net>

Signed-off-by: David S. Miller <davem@davemloft.net>

Signed-off-by: David S. Miller <davem@davemloft.net>

Signed-off-by: David S. Miller <davem@davemloft.net>

Signed-off-by: David S. Miller <davem@davemloft.net>

On the PBM's first bus number, only allow device 0, function 0, to be
poked at with PCI config space accesses.

For some reason, this single device responds to all device numbers.

Also, reduce the verbiage of the debugging log printk's for PCI cfg
space accesses in the SUN4V PCI controller driver, so that it doesn't
overwhelm the slow SUN4V hypervisor console.
Signed-off-by: David S. Miller <davem@davemloft.net>

The trap code was calling itself :-)
Signed-off-by: David S. Miller <davem@davemloft.net>

It just clutters up the log.
Signed-off-by: David S. Miller <davem@davemloft.net>

Signed-off-by: David S. Miller <davem@davemloft.net>

That now gets done as a side effect of taking over the
trap table from OBP.
Signed-off-by: David S. Miller <davem@davemloft.net>

It doesn't like const variables being passed into
"i" constraing asm operations.  It's a bug, but
there is nothing we can really do but work around
it.

Based upon a report from Andrew Morton.
Signed-off-by: David S. Miller <davem@davemloft.net>

Signed-off-by: David S. Miller <davem@davemloft.net>

And check for errors at call sites.
Signed-off-by: David S. Miller <davem@davemloft.net>

Signed-off-by: David S. Miller <davem@davemloft.net>

Signed-off-by: David S. Miller <davem@davemloft.net>

We should dynamically allocate the per-cpu pglist not use
an in-kernel-image datum, since __pa() does not work on
such addresses.

Also, consistently use "u32" for devhandle.
Signed-off-by: David S. Miller <davem@davemloft.net>

Signed-off-by: David S. Miller <davem@davemloft.net>