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  1. 04 Feb, 2020 9 commits
  3. 03 Feb, 2020 4 commits
    • Douglas Anderson's avatar
      dt-bindings: clk: qcom: Fix self-validation, split, and clean cruft · 2a8aa18c
      Douglas Anderson authored 
      The 'qcom,gcc.yaml' file failed self-validation (dt_binding_check)
because it required a property to be either (3 entries big),
(3 entries big), or (7 entries big), but not more than one of those
things.  That didn't make a ton of sense.

This patch splits all of the exceptional device trees (AKA those that
would have needed if/then/else rules) from qcom,gcc.yaml.  It also
cleans up some cruft found while doing that.

After this lands, this worked for me atop clk-next with just the known
error about msm8998:
  for f in \
    Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml \
    Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml \
    Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml \
    Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml \
    Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml \
    Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml \
    Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml \
    Documentation/devicetree/bindings/clock/qcom,gcc.yaml; do \
      ARCH=arm64 make dtbs_check DT_SCHEMA_FILES=$f; \
  done

I then picked this patch atop linux-next (next-20200129) and ran:
  # Delete broken yaml:
  rm Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
  ARCH=arm64 make dt_binding_check | grep 'clock/qcom'
...and that didn't seem to indicate problems.

Arbitrary decisions made (yell if you want changed):
- Left all the older devices (where clocks / clock-names weren't
  specified) in a single file.
- Didn't make clocks "required" for msm8996 but left them as listed.
  This seems a little weird but it matches the old binding.

Misc cleanups as part of this patch:
- Fixed schema id to not have "bindings/" as per Rob [1].
- Listed include files as per Stephen.
- sm8150 was claimed to be same set of clocks as sc7180, but driver
  and dts appear to say that "bi_tcxo_ao" doesn't exist.  Fixed.
- In "apq8064", "#thermal-sensor-cells" was missing the "#".
- Got rid of "|" at the end of top description since spacing doesn't
  matter.
- Changed indentation to consistently 2 spaces (it was 3 in some
  places).
- Added period at the end of protected-clocks description.
- No space before ":".
- Updated sc7180/sm8150 example to use the 'qcom,rpmh.h' include.
- Updated sc7180/sm8150 example to use larger address/size cells as
  per reality.
- Updated sc7180/sm8150 example to point to the sleep_clk rather than
  <0>.
- Made it so that gcc-ipq8074 didn't require #power-domain-cells since
  actual dts didn't have it and I got no hits from:
    git grep _GDSC include/dt-bindings/clock/qcom,gcc-ipq8074.h
- Made it so that gcc-qcs404 didn't require #power-domain-cells since
  actual dts didn't have it and I got no hits from:
    git grep _GDSC include/dt-bindings/clock/qcom,gcc-qcs404.h

Noticed, but not done in this patch (volunteers needed):
- Add "aud_ref_clk" to sm8150 bindings / dts even though I found a
  reference to it in "gcc-sm8150.c".
- Fix node name in actual ipq8074 to be "clock-controller" (it's gcc).
- Since the example doesn't need phandes to exist, in msm8998 could
  just make up places providing some of the clocks currently bogused
  out with <0>.
- On msm8998 clocks are listed as required but current dts doesn't
  have them.

[1] https://lore.kernel.org/r/CAL_Jsq+_2E-bAbP9F6VYkWRp0crEyRGa5peuwP58-PZniVny7w@mail.gmail.com

Fixes: ab91f72e ("clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks")
Signed-off-by: default avatarDouglas Anderson <dianders@chromium.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarJeffrey Hugo <jeffrey.l.hugo@gmail.com>
Link: https://lkml.kernel.org/r/20200203094843.v3.1.I4452dc951d7556ede422835268742b25a18b356b@changeidSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      2a8aa18c
    • Stephen Boyd's avatar
      clk: qcom: Don't overwrite 'cfg' in clk_rcg2_dfs_populate_freq() · 21e157c6
      Stephen Boyd authored 
      The DFS frequency table logic overwrites 'cfg' while detecting the
parent clk and then later on in clk_rcg2_dfs_populate_freq() we use that
same variable to figure out the mode of the clk, either MND or not. Add
a new variable to hold the parent clk bit so that 'cfg' is left
untouched for use later.

This fixes problems in detecting the supported frequencies for any clks
in DFS mode.

Fixes: cc4f6944 ("clk: qcom: Add support for RCG to register for DFS")
Reported-by: default avatarRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200128193329.45635-1-sboyd@kernel.orgTested-by: default avatarRajendra Nayak <rnayak@codeaurora.org>
      21e157c6
    • Stephen Boyd's avatar
      dt/bindings: clk: fsl,plldig: Drop 'bindings' from schema id · fc6a15c8
      Stephen Boyd authored 
      Having 'bindings' in here causes a warning when checking the schema.

 Documentation/devicetree/bindings/clock/fsl,plldig.yaml:
 $id: relative path/filename doesn't match actual path or filename
         expected: http://devicetree.org/schemas/clock/fsl,plldig.yaml#

Remove it.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Wen He <wen.he_1@nxp.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200203052507.93215-2-sboyd@kernel.orgAcked-by: default avatarRob Herring <robh@kernel.org>
      fc6a15c8
    • Stephen Boyd's avatar
      clk: ls1028a: Fix warning on clamp() usage · 0d152f2d
      Stephen Boyd authored 
      These constants are used in clamp() with the value being clamped an
unsigned long. Make them unsigned long defines so that clamp() doesn't
complain about comparing different types.

In file included from include/linux/list.h:9,
                 from include/linux/kobject.h:19,
                 from include/linux/of.h:17,
                 from include/linux/clk-provider.h:9,
                 from drivers/clk/clk-plldig.c:8:
drivers/clk/clk-plldig.c: In function 'plldig_determine_rate':
include/linux/kernel.h:835:29: warning: comparison of distinct pointer types lacks a cast
  835 |   (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
      |
Reported-by: default avatarStephen Rothwell <sfr@canb.auug.org.au>
Cc: Wen He <wen.he_1@nxp.com>
Fixes: d37010a3 ("clk: ls1028a: Add clock driver for Display output interface")
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200203052507.93215-1-sboyd@kernel.org
      0d152f2d
  5. 31 Jan, 2020 7 commits
    • Stephen Boyd's avatar
      Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom',... · db865ee4
      Stephen Boyd authored 
      Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom', 'clk-freescale' and 'clk-qoriq' into clk-next

 - Support for Xilinx Versal platform clks
 - Display clk controller on qcom sc7180
 - Video clk controller on qcom sc7180
 - Graphics clk controller on qcom sc7180
 - CPU PLLs for qcom msm8916
 - Fixes for clk controllers on qcom msm8998 SoCs
 - Move qcom msm8974 gfx3d clk to RPM control
 - Display port clk support on qcom sdm845 SoCs
 - Global clk controller on qcom ipq6018
 - Adjust composite clk to new way of describing clk parents
 - Add a driver for BCLK of Freescale SAI cores

* clk-imx: (32 commits)
  clk: imx: Add support for i.MX8MP clock driver
  dt-bindings: imx: Add clock binding doc for i.MX8MP
  clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based API
  clk: imx: imx8mq: Switch to clk_hw based API
  clk: imx: imx8mm: Switch to clk_hw based API
  clk: imx: imx8mn: Switch to clk_hw based API
  clk: imx: Remove __init for imx_obtain_fixed_clk_hw() API
  clk: imx: gate3: Switch to clk_hw based API
  clk: imx: add hw API imx_clk_hw_mux2_flags
  clk: imx: add imx_unregister_hw_clocks
  clk: imx: clk-composite-8m: Switch to clk_hw based API
  clk: imx: clk-pll14xx: Switch to clk_hw based API
  clk: imx7up: Rename the clks to hws
  clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based
  clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based
  clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw based
  clk: imx: Rename sccg and frac pll register to suggest clk_hw
  clk: imx: imx7ulp composite: Rename to show is clk_hw based
  clk: imx: pllv2: Switch to clk_hw based API
  clk: imx: pllv1: Switch to clk_hw based API
  ...

* clk-ti:
  clk: ti: clkctrl: Fix hidden dependency to node name
  clk: ti: add clkctrl data dra7 sgx
  clk: ti: omap5: Add missing AESS clock
  clk: ti: dra7: fix parent for gmac_clkctrl
  clk: ti: dra7: add vpe clkctrl data
  clk: ti: dra7: add cam clkctrl data
  dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock

* clk-xilinx:
  clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
  clk: zynqmp: Fix divider calculation
  clk: zynqmp: Add support for get max divider
  clk: zynqmp: Warn user if clock user are more than allowed
  clk: zynqmp: Extend driver for versal
  dt-bindings: clock: Add bindings for versal clock driver

* clk-nvidia:
  clk: tegra20/30: Explicitly set parent clock for Video Decoder
  clk: tegra20/30: Don't pre-initialize displays parent clock
  clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation
  clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()
  clk: tegra: Mark fuse clock as critical

* clk-qcom: (35 commits)
  clk: qcom: rpmh: Sort OF match table
  dt-bindings: fix warnings in validation of qcom,gcc.yaml
  dt-binding: fix compilation error of the example in qcom,gcc.yaml
  clk: qcom: Add ipq6018 Global Clock Controller support
  clk: qcom: Add DT bindings for ipq6018 gcc clock controller
  clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks
  clk: qcom: rpmh: Add IPA clock for SC7180
  clk: qcom: rpmh: skip undefined clocks when registering
  clk: qcom: Add video clock controller driver for SC7180
  dt-bindings: clock: Introduce SC7180 QCOM Video clock bindings
  dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings
  clk: qcom: Add graphics clock controller driver for SC7180
  dt-bindings: clock: Introduce SC7180 QCOM Graphics clock bindings
  dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings
  clk: qcom: apcs-msm8916: use clk_parent_data to specify the parent
  clk: qcom: Add display clock controller driver for SC7180
  dt-bindings: clock: Introduce QCOM sc7180 display clock bindings
  dt-bindings: clock: Add YAML schemas for the QCOM DISPCC clock bindings
  clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration
  clk: qcom: alpha-pll: Remove useless read from set rate
  ...

* clk-freescale:
  clk: fsl-sai: new driver
  dt-bindings: clock: document the fsl-sai driver
  clk: composite: add _register_composite_pdata() variants

* clk-qoriq:
  clk: qoriq: add ls1088a hwaccel clocks support
  clk: ls1028a: Add clock driver for Display output interface
  dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings
      db865ee4
    • Stephen Boyd's avatar
      Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas',... · 6e7a9f0c
      Stephen Boyd authored 
      Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas', 'clk-amlogic' and 'clk-allwinner' into clk-next

 - Support dangerous debugfs actions on clks with dead code
 - Convert gpio, fixed-factor, mux, gate, divider basic clks to hw based APIs

* clk-debugfs-danger:
  clk: Add support for setting clk_rate via debugfs

* clk-basic-hw:
  clk: divider: Add support for specifying parents via DT/pointers
  clk: gate: Add support for specifying parents via DT/pointers
  clk: mux: Add support for specifying parents via DT/pointers
  clk: asm9260: Use parent accuracy in fixed rate clk
  clk: fixed-rate: Document that accuracy isn't a rate
  clk: fixed-rate: Add clk flags for parent accuracy
  clk: fixed-rate: Add support for specifying parents via DT/pointers
  clk: fixed-rate: Document accuracy member
  clk: fixed-rate: Move to_clk_fixed_rate() to C file
  clk: fixed-rate: Remove clk_register_fixed_rate_with_accuracy()
  clk: fixed-rate: Convert to clk_hw based APIs
  clk: gpio: Use DT way of specifying parents

* clk-renesas:
  clk: renesas: Prepare for split of R-Car H3 config symbol
  dt-bindings: clock: renesas: cpg-mssr: Fix r8a774b1 typo
  clk: renesas: r7s9210: Add SPIBSC clock
  clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks
  clk: renesas: Remove use of ARCH_R8A7796
  clk: renesas: rcar-gen2: Change multipliers and dividers to u8

* clk-amlogic:
  clk: clarify that clk_set_rate() does updates from top to bottom
  clk: meson: meson8b: make the CCF use the glitch-free mali mux
  clk: meson: pll: Fix by 0 division in __pll_params_to_rate()
  clk: meson: g12a: fix missing uart2 in regmap table
  clk: meson: meson8b: use of_clk_hw_register to register the clocks
  clk: meson: meson8b: don't register the XTAL clock when provided via OF
  clk: meson: meson8b: change references to the XTAL clock to use [fw_]name
  clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier
  clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
  dt-bindings: clock: meson8b: add the clock inputs
  dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding

* clk-allwinner:
  clk: sunxi: a23/a33: Export the MIPI PLL
  clk: sunxi: a31: Export the MIPI PLL
  clk: sunxi-ng: a64: export CLK_CPUX clock for DVFS
  clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
  clk: sunxi-ng: r40: Export MBUS clock
  clk: sunxi: use of_device_get_match_data
      6e7a9f0c
    • Stephen Boyd's avatar
      Merge branches 'clk-uniphier', 'clk-warn-critical', 'clk-ux500', 'clk-kconfig'... · 36bf7a5b
      Stephen Boyd authored 
      Merge branches 'clk-uniphier', 'clk-warn-critical', 'clk-ux500', 'clk-kconfig' and 'clk-at91' into clk-next

 - Warn about critical clks that fail to enable or prepare
 - Detect more PRMCU variants in ux500 driver

* clk-uniphier:
  clk: uniphier: Add SCSSI clock gate for each channel

* clk-warn-critical:
  clk: Warn about critical clks that fail to enable
  clk: Don't try to enable critical clocks if prepare failed
  clk: tegra: Fix double-free in tegra_clk_init()
  clk: samsung: exynos5420: Keep top G3D clocks enabled
  clk: qcom: Avoid SMMU/cx gdsc corner cases
  clk: qcom: gcc-sc7180: Fix setting flag for votable GDSCs
  clk: Move clk_core_reparent_orphans() under CONFIG_OF
  clk: at91: fix possible deadlock
  clk: walk orphan list on clock provider registration
  clk: imx: pll14xx: fix clk_pll14xx_wait_lock
  clk: imx: clk-imx7ulp: Add missing sentinel of ulp_div_table
  clk: imx: clk-composite-8m: add lock to gate/mux

* clk-ux500:
  clk: ux500: Fix up the SGA clock for some variants

* clk-kconfig:
  clk: Fix Kconfig indentation

* clk-at91:
  clk: at91: sam9x60: fix programmable clock prescaler
  clk: at91: sam9x60-pll: adapt PMC_PLL_ACR default value
      36bf7a5b
    • Stephen Boyd's avatar
      Merge branches 'clk-init-allocation', 'clk-unused' and 'clk-register-dt-node-better' into clk-next · 28db9a8c
      Stephen Boyd authored 
       - Let clk_ops::init() return an error code
 - Add a clk_ops::terminate() callback to undo clk_ops::init()

* clk-init-allocation:
  clk: add terminate callback to clk_ops
  clk: let init callback return an error code
  clk: actually call the clock init before any other callback of the clock

* clk-unused:
  clk: bm1800: Remove set but not used variable 'fref'

* clk-register-dt-node-better:
  clk: Use parent node pointer during registration if necessary
      28db9a8c
    • Yangbo Lu's avatar
      clk: qoriq: add ls1088a hwaccel clocks support · a932872f
      Yangbo Lu authored 
      This patch is to add hwaccel clocks information for ls1088a.
Signed-off-by: default avatarYangbo Lu <yangbo.lu@nxp.com>
Link: https://lkml.kernel.org/r/20191216100111.17122-1-yangbo.lu@nxp.comSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      a932872f
    • Wen He's avatar
      clk: ls1028a: Add clock driver for Display output interface · d37010a3
      Wen He authored 
      Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY),
as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable
integer division and range of the display output pixel clock's 27-594MHz.
Signed-off-by: default avatarWen He <wen.he_1@nxp.com>
Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Link: https://lkml.kernel.org/r/20191213083402.35678-2-wen.he_1@nxp.comSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      d37010a3
    • Wen He's avatar
      dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings · 87a5ffb3
      Wen He authored 
      LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to Display
output interface. Add a YAML schema for this.
Signed-off-by: default avatarWen He <wen.he_1@nxp.com>
Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20191213083402.35678-1-wen.he_1@nxp.comSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      87a5ffb3
  7. 28 Jan, 2020 6 commits
  9. 27 Jan, 2020 1 commit
  11. 23 Jan, 2020 6 commits
  13. 22 Jan, 2020 3 commits
    • Stephen Boyd's avatar
      Merge tag 'ti-clk-for-5.6' of... · 660b94e0
      Stephen Boyd authored 
      Merge tag 'ti-clk-for-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into clk-ti

Pull TI clk driver updates from Tero Kristo:

 - cam, vpe and sgx clock support for dra7
 - fix gmac main clock for dra7
 - aess clock support for omap5
 - move dra7-atl clock header to correct location
 - fix hidden node name dependency on clkctrl clocks

* tag 'ti-clk-for-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
  clk: ti: clkctrl: Fix hidden dependency to node name
  clk: ti: add clkctrl data dra7 sgx
  clk: ti: omap5: Add missing AESS clock
  clk: ti: dra7: fix parent for gmac_clkctrl
  clk: ti: dra7: add vpe clkctrl data
  clk: ti: dra7: add cam clkctrl data
  dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock
      660b94e0
    • Stephen Boyd's avatar
      Merge tag 'imx-clk-5.6' of... · 498e1652
      Stephen Boyd authored 
      Merge tag 'imx-clk-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx

Pull i.MX clk driver updates from Shawn Guo:

 - A series from Abel Vesa to do some trivial cleanups which will be
   helpful for i.MX clock driver switching to clk_hw based API
 - A series from Anson Huang to add i.MX8MP clock driver support
 - Disable non-functional divider between pll4_audio_div and
   pll4_post_div on imx6q
 - Fix watchdog2 clock name typo in imx7ulp clock driver
 - A couple of patches from Leonard Crestez to set CLK_GET_RATE_NOCACHE
   flag for DRAM related clocks on i.MX8M SoCs
 - Suppress bind attrs for i.MX8M clock driver to avoid the possibility
   of reloading the driver at runtime
 - Add a big comment in imx8qxp-lpcg driver to tell why
   devm_platform_ioremap_resource() shouldn't be used for the driver
 - A correction on i.MX8MN usb1_ctrl parent clock setting
 - A couple of trivial cleanup on clk-divider-gate driver
 - A series from Peng Fan to convert i.MX8M clock drivers to clk_hw
   based API

* tag 'imx-clk-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (32 commits)
  clk: imx: Add support for i.MX8MP clock driver
  dt-bindings: imx: Add clock binding doc for i.MX8MP
  clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based API
  clk: imx: imx8mq: Switch to clk_hw based API
  clk: imx: imx8mm: Switch to clk_hw based API
  clk: imx: imx8mn: Switch to clk_hw based API
  clk: imx: Remove __init for imx_obtain_fixed_clk_hw() API
  clk: imx: gate3: Switch to clk_hw based API
  clk: imx: add hw API imx_clk_hw_mux2_flags
  clk: imx: add imx_unregister_hw_clocks
  clk: imx: clk-composite-8m: Switch to clk_hw based API
  clk: imx: clk-pll14xx: Switch to clk_hw based API
  clk: imx7up: Rename the clks to hws
  clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based
  clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based
  clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw based
  clk: imx: Rename sccg and frac pll register to suggest clk_hw
  clk: imx: imx7ulp composite: Rename to show is clk_hw based
  clk: imx: pllv2: Switch to clk_hw based API
  clk: imx: pllv1: Switch to clk_hw based API
  ...
      498e1652
    • Stephen Boyd's avatar
      Merge tag 'sunxi-clk-for-5.6' of... · fa9ae305
      Stephen Boyd authored 
      Merge tag 'sunxi-clk-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Maxime Ripard:

Our usual set of patches for sunxi, with a bunch of them required to
enable the MBUS controller, and two patches to enable cpufreq on the
A64.

* tag 'sunxi-clk-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi: a23/a33: Export the MIPI PLL
  clk: sunxi: a31: Export the MIPI PLL
  clk: sunxi-ng: a64: export CLK_CPUX clock for DVFS
  clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
  clk: sunxi-ng: r40: Export MBUS clock
  clk: sunxi: use of_device_get_match_data
      fa9ae305
  15. 20 Jan, 2020 4 commits
    • Tony Lindgren's avatar
      clk: ti: clkctrl: Fix hidden dependency to node name · 6c309052
      Tony Lindgren authored 
      We currently have a hidden dependency to the device tree node name for
the clkctrl clocks. Instead of using standard node name like "clock", we
must use "l4-per-clkctrl" type naming so the clock driver can find the
associated clock domain. Further, if "clk" is specified for a clock node
name, the driver sets TI_CLK_CLKCTRL_COMPAT flag that uses different
logic for the clock name based on the parent node name for the all the
clkctrl clocks for the SoC.

If the clock node naming dependency is not understood, the related
clockdomain is not found, or a wrong one can get used if a clock manager
has multiple clock domains.

As each clkctrl instance represents a single clock domain, let's allow
using domain specific compatible names to specify the clock domain.

This simplifies things and removes the hidden dependency to the node
name. And then later on, after the node names have been standardized,
we can drop the related code for parsing the node names.

Let's also update the binding to use standard "clock" node naming
instead of "clk" and add the missing description for reg.

Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
      6c309052
    • Tony Lindgren's avatar
      clk: ti: add clkctrl data dra7 sgx · 957ad44f
      Tony Lindgren authored 
      This is similar to what we have for omap5 except the gpu_cm address is
different, the mux clocks have one more source option, and there's no
divider clock.

Note that because of the current dts node name dependency for mapping to
clock domain, we must still use "gpu-clkctrl@" naming instead of generic
"clock@" naming for the node. And because of this, it's probably best to
apply the dts node addition together along with the other clock changes.

For accessing the GPU, we also need to configure the interconnect target
module for GPU similar to what we have for omap5, I'll send that change
separately.

Cc: Benoit Parrot <bparrot@ti.com>
Cc: "H. Nikolaus Schaller" <hns@goldelico.com>
Cc: Robert Nelson <robertcnelson@gmail.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
      957ad44f
    • Tony Lindgren's avatar
      clk: ti: omap5: Add missing AESS clock · 364975ee
      Tony Lindgren authored 
      Looks like we're missing AESS clock for omap5. This is similar to what
omap4 has.

Cc: H. Nikolaus Schaller <hns@goldelico.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Reviewed-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
      364975ee
    • Grygorii Strashko's avatar
      clk: ti: dra7: fix parent for gmac_clkctrl · 69e30028
      Grygorii Strashko authored 
      The parent clk for gmac clk ctrl has to be gmac_main_clk (125MHz) instead
of dpll_gmac_ck (1GHz). This is caused incorrect CPSW MDIO operation.
Hence, fix it.

Fixes: dffa9051 ('clk: ti: dra7: add new clkctrl data')
Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
      69e30028
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