- 18 Jul, 2022 3 commits
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YiPeng Chai authored
Add umc v8_10_0 register offset and shift masks header files Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
Alexander Deucher <Alexander.Deucher@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
This is a follow-up cleanup to [1]. See bellow refcount balancing for calling amdgpu_job_submit_direct after this cleanup as far as I calculated. amdgpu_fence_emit dma_fence_init 1 dma_fence_get(fence) 2 rcu_assign_pointer(*ptr, dma_fence_get(fence) 3 ---> amdgpu_job_submit_direct completes before fence signaled amdgpu_sa_bo_free (*sa_bo)->fence = dma_fence_get(fence) 4 amdgpu_job_free dma_fence_put 3 amdgpu_vcn_enc_get_destroy_msg *fence = dma_fence_get(f) 4 dma_fence_put(f); 3 amdgpu_vcn_enc_ring_test_ib dma_fence_put(fence) 2 amdgpu_fence_process dma_fence_put 1 amdgpu_sa_bo_remove_locked dma_fence_put 0 ---> amdgpu_job_submit_direct completes after fence signaled amdgpu_fence_process dma_fence_put 2 amdgpu_job_free dma_fence_put 1 amdgpu_vcn_enc_get_destroy_msg *fence = dma_fence_get(f) 2 dma_fence_put(f); 1 amdgpu_vcn_enc_ring_test_ib dma_fence_put(fence) 0 [1] - https://patchwork.kernel.org/project/dri-devel/cover/20220624180955.485440-1-andrey.grodzovsky@amd.com/Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Suggested-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Sonny Jiang authored
AV1 is only supported on first instance. Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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- 15 Jul, 2022 2 commits
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2022-07-14' of git://anongit.freedesktop.org/drm/drm-misc into drm-next Short summary of fixes: - dma-buf: revert change to fence handling - mgag200: fix PCI register initialization Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/YtAjgcWC1zkNOGWa@linux-uq9g
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Dave Airlie authored
Merge tag 'amd-drm-next-5.20-2022-07-14' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.20-2022-07-14: amdgpu: - DCN3.2 updates - DC SubVP support - DP MST fixes - Audio fixes - DC code cleanup - SMU13 updates - Adjust GART size on newer APUs for S/G display - Soft reset for GFX 11 - Soft reset for SDMA 6 - Add gfxoff status query for vangogh - Improve BO domain pinning - Fix timestamps for cursor only commits - MES fixes - DCN 3.1.4 support - Misc fixes - Misc code cleanup amdkfd: - Simplify GPUVM validation - Unified memory for CWSR save/restore area - fix possible list corruption on queue failure radeon: - Fix bogus power of two warning UAPI: - Unified memory for CWSR save/restore area for KFD Proposed userspace: https://lists.freedesktop.org/archives/amd-gfx/2022-June/080952.htmlSigned-off-by:
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- 14 Jul, 2022 15 commits
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Thomas Zimmermann authored
Remove the read operation from mgag200_init_pci_options(). It was incorrectly added while refactoring the code. Reading the PCI option register clears the register's new value and subsequently leads to re-writing the old value. Signed-off-by:
Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by:
Jocelyn Falempe <jfalempe@redhat.com> Fixes: ce19021f ("drm/mgag200: Move PCI-option setup into model-specific code") Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: Jocelyn Falempe <jfalempe@redhat.com> Cc: Dave Airlie <airlied@redhat.com> Cc: dri-devel@lists.freedesktop.org Link: https://patchwork.freedesktop.org/patch/msgid/20220708072114.13960-1-tzimmermann@suse.de
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Christian König authored
This reverts commit 8f619737. It turned out that this is not correct. Especially the sync_file info IOCTL needs to see even signaled fences to correctly report back their status to userspace. Instead add the filter in the merge function again where it makes sense. Signed-off-by:
Karolina Drobnik <karolina.drobnik@intel.com> Reviewed-by:
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Thomas Zimmermann authored
Backmerging from drm/drm-next for the final fixes that will go into v5.20. Signed-off-by: -
Alex Deucher authored
Several headers were included twice. Fix that. Reported-by:
kernel test robot <yujie.liu@intel.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
André Almeida <andrealmeid@igalia.com> Signed-off-by:
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Roman Li authored
Add support for DCN 3.1.4 in Display Manager Signed-off-by:
Roman Li <roman.li@amd.com> Signed-off-by:
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Roman Li authored
Initialize DMUB for DCN 3.1.4. Use same funcs as DCN31. Signed-off-by:
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Roman Li authored
Add support for DCN 3.1.4 in Display Core Signed-off-by:
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Roman Li authored
DCN 3.1.4 version and family ids Signed-off-by:
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Roman Li authored
Display mode library for DCN 3.1.4 v2: squash in checkpatch fix (Alex) Signed-off-by:
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Roman Li authored
Display Core support for DCN 3.1.4 v2:(squash)fix non-x86 in dc/dcn314/Makefile Properly handle PPC as well. (Alex) v3: minor cleanup (Alex) v4: fix comment (Alex) Signed-off-by:
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Roman Li authored
Clock and SMU interfaces for DCN 3.1.4 Signed-off-by:
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Roman Li authored
IRQ services to support DCN 3.1.4 interrupts. v2: make to_dal_irq_source_dcn314 static (Alex) Signed-off-by:
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Roman Li authored
Register headers for the following IPs: - DCN 3.1.4 - DPCS 3.1.4 v2:(squash) clean up (Alex) Signed-off-by:
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Michel Dänzer authored
Requires enabling the vblank machinery for them. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2030Acked-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
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Leo Li authored
When pinning a buffer, we should check to see if there are any additional restrictions imposed by bo->preferred_domains. This will prevent the BO from being moved to an invalid domain when pinning. For example, this can happen if the user requests to create a BO in GTT domain for display scanout. amdgpu_dm will allow pinning to either VRAM or GTT domains, since DCN can scanout from either or. However, in amdgpu_bo_pin_restricted(), pinning to VRAM is preferred if there is adequate carveout. This can lead to pinning to VRAM despite the user requesting GTT placement for the BO. v2: Allow the kernel to override the domain, which can happen when exporting a BO to a V4L camera (for example). Signed-off-by:Leo Li <sunpeng.li@amd.com> Reviewed-by:
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- 13 Jul, 2022 20 commits
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Alex Deucher authored
The indentation is screwed up. I'm not sure quite how the logic should flow. Someone more familiar with this code should verify this. Reviewed-by:
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André Almeida authored
Implement function to get current GFXOFF status for vangogh. Signed-off-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Melissa Wen authored
Check the value of per_pixel_alpha to decide whether the Coverage pixel blend mode is applicable or not. Fixes: 76818cdd ("drm/amd/display: add Coverage blend mode for overlay plane") Reported-by:
kernel test robot <lkp@intel.com> Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Yefim Barashkin authored
divide error: 0000 [#1] SMP PTI CPU: 3 PID: 78925 Comm: tee Not tainted 5.15.50-1-lts #1 Hardware name: MSI MS-7A59/Z270 SLI PLUS (MS-7A59), BIOS 1.90 01/30/2018 RIP: 0010:smu_v11_0_set_fan_speed_rpm+0x11/0x110 [amdgpu] Speed is user-configurable through a file. I accidentally set it to zero, and the driver crashed. Reviewed-by:
Yefim Barashkin <mr.b34r@kolabnow.com> Signed-off-by:
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Mario Kleiner authored
Various DCE versions had trouble with 36 bpp lb depth, requiring fixes, last time in commit 353ca0fa ("drm/amd/display: Fix 10bit 4K display on CIK GPUs") for DCE-8. So far >= DCE-11.2 was considered ok, but now I found out that on DCE-11.2 it causes dithering when there shouldn't be any, so identity pixel passthrough with identity gamma LUTs doesn't work when it should. This breaks various important neuroscience applications, as reported to me by scientific users of Polaris cards under Ubuntu 22.04 with Linux 5.15, and confirmed by testing it myself on DCE-11.2. Lets only use depth 36 for DCN engines, where my testing showed that it is both necessary for high color precision output, e.g., RGBA16 fb's, and not harmful, as far as more than one year in real-world use showed. DCE engines seem to work fine for high precision output at 30 bpp, so this ("famous last words") depth 30 should hopefully fix all known problems without introducing new ones. Successfully retested on DCE-11.2 Polaris and DCN-1.0 Raven Ridge on top of Linux 5.19.0-rc2 + drm-next. Fixes: 353ca0fa ("drm/amd/display: Fix 10bit 4K display on CIK GPUs") Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Tested-by:
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Alex Deucher authored
Not used outside of dc_dmub_srv.c. Reported-by:
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Alex Deucher authored
Drop execute. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2085Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Kent Russell authored
The initialism of RunList Controller is RLC, not RCL Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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Aric Cyr authored
This version brings along following fixes: - Fixes for MST, MPO, PSRSU, DP 2.0, Freesync and others - Add register offsets of NBI and DCN. - Improvement of ALPM - Removing assert statement for Linux DM - Re-implementing ARGB16161616 pixel format Acked-by:
Solomon Chiu <solomon.chiu@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Samson Tam authored
[Why] With single display odm 2:1 policy, when moving windowed MPO across the display, we experience a momentary lag when we move between the centre of the display and the right half of the display. This is caused by the MPO pipe being reallocated when it crosses this boundary [How] Handle two cases: 1. if the head pipe has a MPO pipe already allocated in the old context, then use that pipe if it is available in the current context 2. if the head pipe is on the left side, check the right side to see if it has a MPO pipe already allocated. If so, don't use that pipe if it is selected as the idle pipe in the current context Add new function pointer called .acquire_idle_pipe_for_head_pipe that will pass in the head pipe and handle case 1 Add find_idle_secondary_pipe_check_mpo() to handle case 2 if we don't hit case 1. In dc_add_plane_to_context(), start with head pipe and check case 1 and 2 in call acquire_free_pipe_for_head(). If we are on the right side of the display, check case 1 again by passing in right side pipe as the new head in call acquire_free_pipe_for_head(). Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by:
Samson Tam <Samson.Tam@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why&How] Add a field to store the NBIO IP offset for use with runtime offset calculation Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Harry Wentland authored
[Why&How] Add a field to store the DCN IP offset for use with runtime offset calculation This offset is indexed using reg*_BASE_IDX for the corresponding group of registers. For example, address of DIG_BE_CNTL instance 0 is calculated like: dcn_reg_offsets[regDIG0_DIG_BE_CNTL_BASE_IDX] + regDIG0_DIG_BE_CNTL. {dcn,nbio}_reg_offsets are used only for the ASICs for which runtime initializaion of offsets are enabled through the modified SR* macros that contain an additional REG_STRUCT element in the macro definition. DCN3.5+ will fail dc_create() if {dcn,nbio}_reg_offsets are null. They are applicable starting with DCN32/321 and are not used for ASICs upstreamed before them. ASICs before DCN32/321 will not contain any computation that involves {dcn,nbio}_reg_offsets. For them, the address/offset computation is done during compile time. This is evident from the BASE_INNER definition for compile time vs run time initialization: Compile time init: #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg Run time init: #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] BASE_INNER macro is local to each dcnxx_resource.c and hence different ASICs can have either runtime or compile time initialization of offsets. The computation of offset is done for registers all at once during driver load and hence it does not introduce any performance overhead during normal operation. Reviewed-by: -
Charlene Liu authored
[why] insert log for debug use. v2: squash in fix (Alex) Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
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Wayne Lin authored
[Why & How] There is chance we change dc state while calling dc_link_detect(). As the result of that, grab the dm.dc_lock before detecting link. Reviewed-by:
Hersen Wu <hersen.wu@amd.com> Acked-by:
Wayne Lin <Wayne.Lin@amd.com> Tested-by:
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Ethan Wellenreiter authored
[Why] ABGR16161616 colour format was added to dcn10/20/30, and set any ARGB16161616 to the same value as it (26). As such, the HDR10 Green Point y value was too far off of the EDID stated value for DisplayPort. [How] Added back the pixel format as 22 for ARGB16161616 for dcn10/20/30. Reviewed-by:
Reza Amini <reza.amini@amd.com> Acked-by:
Ethan Wellenreiter <Ethan.Wellenreiter@amd.com> Tested-by:
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Aric Cyr authored
Acked-by:
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Jun Lei authored
[why] Unbounded request logic in resource/DML has some issues where unbounded request is being enabled incorrectly. SW today enables unbounded request unconditionally in hardware, on the assumption that HW can always support it in single pipe scenarios. This worked until now because the same assumption is made in DML. A new DML update is needed to fix a bug, where there are single pipe scenarios where unbounded cannot be enabled, and this change in DML needs to be ported in, and dcn32 resource logic fixed. [how] First, dcn32_resource should program unbounded req in HW according to unbounded req enablement output from DML, as opposed to DML input Second, port in DML1 update which disables unbounded req in some scenarios to fix an issue with poor stutter performance Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
Jun Lei <jun.lei@amd.com> Tested-by:
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Jack Xiao authored
Port aggregated doorbell support to gfx11. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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Jack Xiao authored
Port aggregated doorbell support to sdma6. Signed-off-by:
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Le Ma authored
Ring aggregated doorbel to make unmapped queue scheduled in mes firmware. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
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