- 28 Nov, 2014 7 commits
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git://git.infradead.org/linux-mvebuArnd Bergmann authored
Pull "mvebu SoC changes for v3.19" from Jason Cooper: - Armada 38x - Implement CPU hotplug support - Armada 375 - Remove Z1 stepping support (limited dist. of SoC) * tag 'mvebu-soc-3.19' of git://git.infradead.org/linux-mvebu: ARM: mvebu: Implement the CPU hotplug support for the Armada 38x SoCs ARM: mvebu: Fix the secondary startup for Cortex A9 SoC ARM: mvebu: Move SCU power up in a function ARM: mvebu: Clean-up the Armada XP support ARM: mvebu: update comments in coherency.c ARM: mvebu: remove Armada 375 Z1 workaround for I/O coherency ARM: mvebu: remove unused register offset definition ARM: mvebu: disable I/O coherency on non-SMP situations on Armada 370/375/38x/XP ARM: mvebu: make the coherency_ll.S functions work with no coherency fabric ARM: mvebu: Remove thermal quirk for A375 Z1 revision ARM: mvebu: add missing of_node_put() call in coherency.c ARM: orion: Fix for certain sequence of request_irq can cause irq storm ARM: mvebu: armada xp: Generalize use of i2c quirk Signed-off-by:Arnd Bergmann <arnd@arndb.de>
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Oleksij Rempel authored
Since there is no public documentation, this patch also provide register offsets for different UART units on this SoC. Signed-off-by:
Oleksij Rempel <linux@rempel-privat.de> Signed-off-by:
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Oleksij Rempel authored
it is low cost (?) SoC targeted for market in China and India which trying to compete with AT91SAM9G25. Here is some info: http://www.alphascale.com/index.asp?ics/615.html One of products: http://www.aliexpress.com/store/product/2014-hot-sales-FREE-SHIPPING-new-Purple-core-ARM9-development-board-ASM9260T-SDRAM-power-line/433637_1931495721.html In some cases this SoC looks similar to iMX23/iMX28. But currently it makes no sense to merge mach code of this devices. Especially because most differences are already collected mach-mxs folder. Signed-off-by:
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Arnd Bergmann authored
Merge tag 'imx-soc-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc Pull "The i.MX SoC update for 3.19" from Shawn Guo - Update i.MX6 suspend code to check DDR instead of CPU type, as the difference we need to handle is between LPDDR2 and DDR3, not SoCs. - Set anatop properly for LPDDR2 in DSM mode - Add support for new SoC LS1021A which integrates dual Cortex-A7 - Add ENET initialization for i.MX6SX platform - Add cpufreq support for i.MX53 platform - Add a SNVS based poweroff driver for i.MX6 platforms - Use ARM Global Timer as clocksource on VF610 Note: the change set is built on top of tag imx-fixes-3.18-2 to resolve a conflict on file arch/arm/mach-imx/clk-vf610.c. * tag 'imx-soc-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: power: reset: imx-snvs-poweroff: add power off driver for i.mx6 ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A ARM: imx: clk-vf610: get input clocks from assigned clocks ARM: imx: Add Freescale LS1021A SMP support ARM: imx: Add initial support for Freescale LS1021A ARM: imx53: add cpufreq support ARM: imx53: clk: add ARM clock ARM: imx: add CPU clock type ARM: imx5: add step clock, used when reprogramming PLL1 ARM: imx: add enet init for i.mx6sx ARM: imx6sx: add imx6sx iomux-gpr field define ARM: vf610: Add ARM Global Timer clocksource option ARM: imx: add anatop settings for LPDDR2 when enter DSM mode ARM: imx: replace cpu type check with ddr type check ARM: imx: Fix the removal of CONFIG_SPI option ARM: imx: clk-vf610: define PLL's clock tree Signed-off-by; Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge (part of) tag 'omap-for-v3.19/hwmod-and-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc SoC related changes for omaps including hwmod clean-up for DSS, and hwmod data for more UARTs and ADC. Also few defconfig changes to enable devices found on am335x and am437x. [arnd: I removed the defconfig changes from the branch in order to cherry-pick them onto the next/defconfig branch, but I did not change the other commits] * commit '29c4ce17': ARM: dts: cm-t3x30: add keypad support ARM: OMAP2+: hwmod: AM43x: add hwmod support for ADC on AM43xx ARM: DRA7: hwmod data: Add missing UART hwmod data ARM: dts: omap4.dtsi: remove dss_fck ARM: OMAP4: fix RFBI iclk ARM: OMAP4: hwmod: use MODULEMODE properly ARM: OMAP4: hwmod: set DSS submodule parent hwmods ARM: OMAP5: hwmod: set DSS submodule parent hwmods ARM: OMAP2+: hwmod: add parent_hwmod support Signed-off-by:
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Arnd Bergmann authored
Merge tag 'samsung-pm-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc Pull "Samsung PM 3rd updates for v3.19" from Kukjin Kim: - exynos3250 : add PMU support - PMU refactoring : move restart code into PMU driver : move restart code for exynos440 into clk driver - use u8 for val[] in struct exynos_pmu_conf Note that this branch is based on tags/samsung-exynos-v3.19 * tag 'samsung-pm-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf ARM: EXYNOS: move restart code into pmu driver clk: exynos5440: move restart code into clock driver ARM: EXYNOS: add exynos3250 PMU support Signed-off-by:
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Arnd Bergmann authored
Merge tag 'samsung-exynos-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc Pull "Samsung exynos updates in arch/arm/mach-exynos/ for v3.19" from Kukjin Kim: - add SOC_EXYNOS4415 config to be used in audio driver - add support platform driver for exynos PMU - move PMU specific definitions from common.h to exynos-pmu.h - for exynos5420, add support PMU and Suspend-to-RAM use MCPM call backs and call regulator core suspend prepare and finish functions NOTE: including v3.19-next/non-critical-fixes, v3.19-next/cleanup-samsung and v3.19-next/pm-samsung-2 branches * tag 'samsung-exynos-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: Call regulator core suspend prepare and finish functions ARM: EXYNOS: Use MCPM call-backs to support S2R on exynos5420 ARM: EXYNOS: Add Suspend-to-RAM support for exynos5420 ARM: EXYNOS: Add PMU support for exynos5420 ARM: EXYNOS: Move PMU specific definitions from common.h ARM: EXYNOS: Add platform driver support for Exynos PMU ARM: EXYNOS: Add support for exynos4415 SoC ARM: EXYNOS: fix typo in static struct name "exynos5_list_diable_wfi_wfe" ARM: EXYNOS: Fix CPU idle clock down after CPU off ARM: EXYNOS: Remove unneeded __ref annotation for cpu_die function ARM: EXYNOS: Move code from hotplug.c to platsmp.c Signed-off-by:
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- 26 Nov, 2014 1 commit
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Bartlomiej Zolnierkiewicz authored
Values stored in val[] are never bigger than a byte. text data bss dec hex filename 7716 3692 8 11416 2c98 arch/arm/mach-exynos/pmu.o.before 5436 1908 8 7352 1cb8 arch/arm/mach-exynos/pmu.o.after Cc: Pankaj Dubey <pankaj.dubey@samsung.com> Cc: Amit Daniel Kachhap <amit.daniel@samsung.com> Signed-off-by:
Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by:
Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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- 23 Nov, 2014 15 commits
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Robin Gong authored
This driver register pm_power_off with snvs power off function. If your boards NOT use PMIC_ON_REQ to turn on/off external pmic, or use other pin to do, please disable the driver in dts, otherwise, your pm_power_off maybe overwrote by this driver. Signed-off-by:
Robin Gong <b38343@freescale.com> Acked-By:
Sebastian Reichel <sre@kernel.org> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Arnd Bergmann authored
The newly introduced LS1021A SoC selects CONFIG_SOC_FSL, which is originally symbol used for the PowerPC based platforms and guards lots of code that does not build on ARM. This breaks allmodconfig, so let's remove it for now, until either all those drivers are fixed or they use a dependency on IMX instead. Signed-off-by:
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Stefan Agner authored
With the clock assignment device tree changes, the clocks get initialized properly but the search for those clocks fails with errors: [ 0.000000] i.MX clk 4: register failed with -17 [ 0.000000] i.MX clk 5: register failed with -17 This is because the module can't find those clocks anymore, and tries to initialize fixed clocks with the same name. Get the clock modules input clocks from the assigned clocks by default by using of_clk_get_by_name(). If this function returns not a valid clock, fall back to the old behaviour and search the input clock from the device tree's /clocks/$name node. Signed-off-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
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Jingchang Lu authored
Freescale LS1021A SoCs deploy two cortex-A7 processors, this adds bring-up support for the secondary core. Signed-off-by:
Jingchang Lu <b35083@freescale.com> Signed-off-by:
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Jingchang Lu authored
The LS1021A SoC is a dual-core Cortex-A7 based processor, this adds the initial support for it. Signed-off-by:
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Lucas Stach authored
Instanciate device for the generic cpufreq-dt driver. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
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Lucas Stach authored
The ARM clock is a virtual clock feeding the ARM partition of the SoC. It controls multiple other clocks to ensure the right sequencing when cpufreq changes the CPU clock rate. Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Lucas Stach authored
This implements a virtual clock used to abstract away all the steps needed in order to change the ARM clock, so we don't have to push all this clock handling into the cpufreq driver. While it will be used for i.MX53 at first it is generic enough to be used on i.MX6 later on. Signed-off-by:
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Lucas Stach authored
This is the bypass clock used to feed the ARM partition while we reprogram PLL1 to another rate. Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
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Fugang Duan authored
Add enet init for i.mx6sx: - Add phy ar8031 fixup - Set enet clock source from internal PLL Signed-off-by:
Fugang Duan <B38611@freescale.com> Signed-off-by:
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Fugang Duan authored
Add imx6sx iomux-gpr register field define in "imx6q-iomuxc-gpr.h" header file, which is not fully define all iomux-gpr registers and fields, only align with freescale internal tree related GPR macro define. Signed-off-by:
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Stefan Agner authored
Add the ARM Global Timer as clocksource/scheduler clock option and use it as default scheduler clock. This leaves the PIT timer for other users e.g. the secondary Cortex-M4 core. Also, the Global Timer has double the precission (running at pheripheral clock compared to IPG clock) and a 64-bit incrementing counter register. We still keep the PIT timer as an secondary option in case the ARM Global Timer is not available. Signed-off-by:
Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by:
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Anson Huang authored
For LPDDR2 platform, no need to enable weak2P5 in DSM mode, it can be pulled down to save power(~0.65mW). And per design team's recommendation, we should disconnect VDDHIGH and SNVS in DSM mode on i.MX6SL. Signed-off-by:
Anson Huang <b20788@freescale.com> Signed-off-by:
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Anson Huang authored
As the DDR/IO and MMDC setting are different on LPDDR2 and DDR3, we used cpu type to decide how to do these settings in suspend before which is NOT flexible, take i.MX6SL for example, although it has LPDDR2 on EVK board, but users can also use DDR3 on other boards, so it is better to read the DDR type from MMDC then decide how to do related settings. Signed-off-by:
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Shawn Guo authored
The i.MX fixes for 3.18, 2nd round: - Fix a regression on Vybrid platform which is caused by commit dc4805c2 (ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver), and results in a missing configuration on PLL clocks. - Fix a regression with i.MX defconfig files where CONFIG_SPI option gets lost accidentally.
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- 22 Nov, 2014 14 commits
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Pankaj Dubey authored
Let's register restart handler from PMU driver for restart functionality. So that we can remove restart hooks from machine specific file, and thus moving ahead when PMU moved to driver folder, this functionality can be reused for ARM64 based Exynos SoC's. Signed-off-by:
Pankaj Dubey <pankaj.dubey@samsung.com> Acked-by:
Guenter Roeck <linux@roeck-us.net> Tested-by:
Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by:
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Pankaj Dubey authored
Let's register restart handler for Exynos5440 from it's clock driver for restart functionality. So that we can cleanup restart hooks from machine specific file. CC: Sylwester Nawrocki <s.nawrocki@samsung.com> CC: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by:
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Bartlomiej Zolnierkiewicz authored
This patch prepares the PMU code for the future: - suspend/resume (S2R) support - cpuidle AFTR/W-AFTR modes support on Exynos3250. Cc: Vikas Sajjan <vikas.sajjan@samsung.com> Reviewed-by:
Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by:
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Gregory CLEMENT authored
This commit implements the CPU hotplug support for the Marvell Armada 38x platform. Similarly to what was done for the Armada XP, this commit: * Implements the ->cpu_die() function of SMP operations by calling armada_38x_do_cpu_suspend() to enter the deep idle state for CPUs going offline. * Implements a dummy ->cpu_kill() function, simply needed for the kernel to know we have CPU hotplug support. * The mvebu_cortex_a9_boot_secondary() function makes sure to wake up the CPU if waiting in deep idle state by sending an IPI before deasserting the CPUs from reset. This is because mvebu_cortex_a9_boot_secondary() is now used in two different situations: for the initial boot of secondary CPUs (where CPU reset deassert is used to wake up CPUs) and for CPU hotplug (where an IPI is used to take CPU out of deep idle). * At boot time, we exit from the idle state in the ->smp_secondary_init() hook. This commit has been tested using CPU hotplug through sysfs (/sys/devices/system/cpu/cpuX/online) and using kexec. Signed-off-by:Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by:
Jason Cooper <jason@lakedaemon.net>
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Gregory CLEMENT authored
During the secondary startup the SCU was assumed to be in normal mode. It is not always the case, and especially after a kexec. This commit adds the needed sequence to put the SCU in normal mode. Signed-off-by:
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Gregory CLEMENT authored
This will allow reusing the same function in the secondary_startup for the Cortex A9 SoC. Signed-off-by:
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Gregory CLEMENT authored
This patch removes the unneeded include of the armada-370-xp.h header. It also moves some declarations from this file into more accurate places. Finally, it also adds a comment explaining that we can't remove yet the smp field in the dt machine struct due to backward compatibly of the device tree. In a few releases, when the old device tree will be obsolete, we will be able to remove the smp field and then the armada-370-xp.h header. Signed-off-by:
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Thomas Petazzoni authored
The coherency.c top-level comment mentions that it supports the coherency fabric for Armada 370 and XP, but it also supports the coherency fabric on Armada 375 and 38x, so this commit updates the comment accordingly. Signed-off-by:
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Thomas Petazzoni authored
This reverts commit 5ab5afd8 ("ARM: mvebu: implement Armada 375 coherency workaround"), since we are removing the support for the very early Z1 revision of the Armada 375 SoC. This commit is an exact revert, with two exceptions: - minor adaptations needed due to other changes that have taken place in coherency.c since the original commit - keep the definition of pr_fmt. This shouldn't originally have been part of the Armada 375 Z1 workaround commit since it had nothing to do with it. Signed-off-by:
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Thomas Petazzoni authored
Since commit b21dcafe ("arm: mvebu: remove dependency of SMP init on static I/O mapping"), the COHERENCY_FABRIC_CFG_OFFSET register offset definition is no longer used, so this commit removes it. Signed-off-by:
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Thomas Petazzoni authored
Enabling the hardware I/O coherency on Armada 370, Armada 375, Armada 38x and Armada XP requires a certain number of conditions: - On Armada 370, the cache policy must be set to write-allocate. - On Armada 375, 38x and XP, the cache policy must be set to write-allocate, the pages must be mapped with the shareable attribute, and the SMP bit must be set Currently, on Armada XP, when CONFIG_SMP is enabled, those conditions are met. However, when Armada XP is used in a !CONFIG_SMP kernel, none of these conditions are met. With Armada 370, the situation is worse: since the processor is single core, regardless of whether CONFIG_SMP or !CONFIG_SMP is used, the cache policy will be set to write-back by the kernel and not write-allocate. Since solving this problem turns out to be quite complicated, and we don't want to let users with a mainline kernel known to have infrequent but existing data corruptions, this commit proposes to simply disable hardware I/O coherency in situations where it is known not to work. And basically, the is_smp() function of the kernel tells us whether it is OK to enable hardware I/O coherency or not, so this commit slightly refactors the coherency_type() function to return COHERENCY_FABRIC_TYPE_NONE when is_smp() is false, or the appropriate type of the coherency fabric in the other case. Thanks to this, the I/O coherency fabric will no longer be used at all in !CONFIG_SMP configurations. It will continue to be used in CONFIG_SMP configurations on Armada XP, Armada 375 and Armada 38x (which are multiple cores processors), but will no longer be used on Armada 370 (which is a single core processor). In the process, it simplifies the implementation of the coherency_type() function, and adds a missing call to of_node_put(). Signed-off-by:
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Thomas Petazzoni authored
The ll_add_cpu_to_smp_group(), ll_enable_coherency() and ll_disable_coherency() are used on Armada XP to control the coherency fabric. However, they make the assumption that the coherency fabric is always available, which is currently a correct assumption but will no longer be true with a followup commit that disables the usage of the coherency fabric when the conditions are not met to use it. Therefore, this commit modifies those functions so that they check the return value of ll_get_coherency_base(), and if the return value is 0, they simply return without configuring anything in the coherency fabric. The ll_get_coherency_base() function is also modified to properly return 0 when the function is called with the MMU disabled. In this case, it normally returns the physical address of the coherency fabric, but we now check if the virtual address is 0, and if that's case, return a physical address of 0 to indicate that the coherency fabric is not enabled. Signed-off-by:
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Jason Cooper authored
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Dmitry Lifshitz authored
Add twl4030 matrtix keypad support. Signed-off-by:
Dmitry Lifshitz <lifshitz@compulab.co.il> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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- 21 Nov, 2014 3 commits
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Tony Lindgren authored
Merge tag 'for-v3.19/omap-b2' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.19/soc Several more OMAP patches targeted for v3.19. They include: - OMAP4/5: DSS hwmod cleanup patches from Tomi Valkeinen. - DRA7xx: hwmod data support for UARTs 7 through 10. - AM43xx: hwmod data support for the onboard ADC. Basic build, boot, and PM test reports are here: http://www.pwsan.com/omap/testlogs/omap-b-for-v3.19/20141121110550/ Note that I cannot test the DRA7xx or AM43xx patches, since I do not have these boards.
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Paul Walmsley authored
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Vignesh R authored
This patch adds hwmod support for ADC on AM43xx. Since clockdomain and offsets of adc_tsc are different from AM33xx, ADC data has been directly added to AM43xx hwmod file. Signed-off-by:
Vignesh R <vigneshr@ti.com> [paul@pwsan.com: fixed spelling of "Anolog"; converted spaces to tabs] Signed-off-by:
Paul Walmsley <paul@pwsan.com>
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