- 06 Apr, 2016 40 commits
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Tim Gardner authored
Ignore: yes Signed-off-by:Tim Gardner <tim.gardner@canonical.com>
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Andy Whitcroft authored
BugLink: http://bugs.launchpad.net/bugs/1555033Signed-off-by:
Andy Whitcroft <apw@canonical.com>
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Andy Whitcroft authored
BugLink: http://bugs.launchpad.net/bugs/1555033Signed-off-by:
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Andy Whitcroft authored
BugLink: http://bugs.launchpad.net/bugs/1555033Signed-off-by:
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Andy Whitcroft authored
BugLink: http://bugs.launchpad.net/bugs/1555033Signed-off-by:
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Tim Gardner authored
Signed-off-by: -
Tim Gardner authored
The diff cannot represent when files are moved. Signed-off-by: -
Tim Gardner authored
Ignore: yes Signed-off-by: -
Tim Gardner authored
Signed-off-by: -
Ville Syrjälä authored
BugLink: http://bugs.launchpad.net/bugs/1543683 Looks like g4x hpd live status bits actually agree with the spec. At least they do on the machine I have, and apparently on Nick Bowler's g4x as well. So gm45 may be the only platform where they don't agree. At least that seems to be the case based on the (somewhat incomplete) logs/dumps in [1], and Daniel has also tested this on his gm45 sometime in the past. So let's change the bits to match the spec on g4x. That actually makes the g4x bits identical to vlv/chv so we can just share the code between those platforms, leaving gm45 as the special case. [1] https://bugzilla.kernel.org/show_bug.cgi?id=52361 Cc: Shashank Sharma <shashank.sharma@intel.com> Cc: Sonika Jindal <sonika.jindal@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Nick Bowler <nbowler@draconx.ca> References: https://lists.freedesktop.org/archives/dri-devel/2016-February/100382.htmlReported-by:
Nick Bowler <nbowler@draconx.ca> Cc: stable@vger.kernel.org Fixes: 237ed86c ("drm/i915: Check live status before reading edid") Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455127145-20087-1-git-send-email-ville.syrjala@linux.intel.comReviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 0780cd36) Signed-off-by:
Jani Nikula <jani.nikula@intel.com> (back ported from commit 8d409cb3) Signed-off-by:
Joseph Salisbury <joseph.salisbury@canonical.com>
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Andy Whitcroft authored
BugLink: http://bugs.launchpad.net/bugs/1543165Signed-off-by:
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Parthasarathy Bhuvaragan authored
commit 4d5cfcba ('tipc: fix connection abort during subscription cancel'), removes the check for a valid subscription before calling tipc_nametbl_subscribe(). This will lead to a nullptr exception when we process a subscription cancel request. For a cancel request, a null subscription is passed to tipc_nametbl_subscribe() resulting in exception. In this commit, we call tipc_nametbl_subscribe() only for a valid subscription. Fixes: 4d5cfcba ('tipc: fix connection abort during subscription cancel') Reported-by:
Anders Widell <anders.widell@ericsson.com> Signed-off-by:
Parthasarathy Bhuvaragan <parthasarathy.bhuvaragan@ericsson.com> Acked-by:
Jon Maloy <jon.maloy@ericsson.com> Signed-off-by:
David S. Miller <davem@davemloft.net> (cherry picked from commit 4de13d7e) Signed-off-by:
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Linus Torvalds authored
BugLink: http://bugs.launchpad.net/bugs/1554608 This reverts commit dbb17a21. It turns out that commit can cause problems for systems with multiple GPUs, and causes X to hang on at least a HP Pavilion dv7 with hybrid graphics. This got noticed originally in 4.4.4, where this patch had already gotten back-ported, but 4.5-rc7 was verified to have the same problem. Alexander Deucher says: "It looks like you have a muxed system so I suspect what's happening is that one of the display is being reported as connected for both the IGP and the dGPU and then the desktop environment gets confused or there some sort problem in the detect functions since the mux is not switched to the dGPU. I don't see an easy fix unless Dave has any ideas. I'd say just revert for now" Reported-by:
Jörg-Volker Peetz <jvpeetz@web.de> Acked-by:
Alexander Deucher <Alexander.Deucher@amd.com> Cc: Dave Airlie <airlied@gmail.com> Cc: stable@kernel.org # wherever dbb17a21 got back-ported Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org> (cherry picked from commit 256faedc) Signed-off-by:
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Andrew Pinski authored
On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI instructions may cause the icache to become corrupted if it contains data for a non-current ASID. This patch implements the workaround (which invalidates the local icache when switching the mm) by using code patching. Signed-off-by:
Andrew Pinski <apinski@cavium.com> Signed-off-by:
David Daney <david.daney@cavium.com> Reviewed-by:
Will Deacon <will.deacon@arm.com> Signed-off-by:
Catalin Marinas <catalin.marinas@arm.com> (cherry picked from linux-next commit 104a0c02) [ dannf: dropped Documentation/ change to file that didn't exist in v4.4; Adjusted cpu errata numbers for v4.4 ] Signed-off-by:
dann frazier <dann.frazier@canonical.com> Signed-off-by:
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Tirumalesh Chalamarla authored
Due to Errata in ThunderX, HOST_IRQ_STAT should be cleared before leaving the interrupt handler. The patch attempts to satisfy the need. Changes from V2: - removed newfile - code is now under CONFIG_ARM64 Changes from V1: - Rebased on top of libata/for-4.6 - Moved ThunderX intr handler to new file tj: Minor adjustments to comments. Signed-off-by:Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com> Signed-off-by:
Tejun Heo <tj@kernel.org> (cherry picked from commit d243bed3) Signed-off-by:
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Sunil Goutham authored
On Thunderx pass 1.x and pass2 due to a HW errata default CQ DROP_LEVEL of 0x80 is not sufficient to avoid CQ_WR_FULL Qset error when packets are being received at >20Mpps resulting in complete stall of packet reception. This patch will configure it to 0x100 which is what is expected by HW on Thunderx. On future passes of thunderx and other chips HW default/reset value will be 0x100 or higher hence not overwritten. Signed-off-by:
Jerin Jacob <jerin.jacob@caviumnetworks.com> Signed-off-by:
Sunil Goutham <sgoutham@cavium.com> Signed-off-by:
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dann frazier authored
Signed-off-by:
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Andy Whitcroft authored
BugLink: http://bugs.launchpad.net/bugs/1543165Signed-off-by:
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Andy Whitcroft authored
BugLink: http://bugs.launchpad.net/bugs/1543165Signed-off-by:
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Andy Whitcroft authored
BugLink: http://bugs.launchpad.net/bugs/1543165Signed-off-by:
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Andy Whitcroft authored
BugLink: http://bugs.launchpad.net/bugs/1543165Signed-off-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 I missed this when cleaning up the vce pg handling. Signed-off-by:
Alberto Milone <alberto.milone@canonical.com> Signed-off-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Enable vce and uvd pg based on single set of pg flags. Reviewed-by:
Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Enable vce and uvd pg based on single set of pg flags. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 So they can be used by powerplay. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Leftover from radeon. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Needed to pass the cg and pg info to powerplay. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Not working reliably yet. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Not working reliably yet. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Not working reliably yet. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Not working reliably yet. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Don't do anything if the uvd cg flags are not set. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 It was already disabled elsewhere, make it offical. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Don't attempt to start/stop the vce block if pg is disabled. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Don't attempt to start/stop the uvd block if pg is disabled. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 We already query this at driver init, so use that info. Also handles virtualization cases. Reviewed-by:
monk liu <monk.liu@amd.com> Signed-off-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Pcie registers may not be available in a virtualized environment. Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Allows the user to force the supported pcie gen and lane config on both the asic and the chipset. Useful for debugging pcie problems and for virtualization where we may not be able to query the pcie bridge caps. Default to: gen: chipset 1/2, asic 1/2/3 lanes: 1/2/4/8/16 v2: fix bare metal case Reviewed-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 Doesn't work properly yet. Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Sonny Jiang <sonny.jiang@amd.com> Signed-off-by:
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Alex Deucher authored
BugLink: http://bugs.launchpad.net/bugs/1546572 The smc doesn't handle it. Reviewed-by:
Ken Wang <Qingqing.Wang@amd.com> Reviewed-by:
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