- 29 Mar, 2021 25 commits
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Linus Walleij authored
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Linus Walleij authored
Merge tag 'intel-pinctrl-v5.13-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.13-1 * Don't disable disabled IRQs in the handler * Fix the base calculation for groups defined by size The following is an automated git shortlog grouped by driver: intel: - No need to disable IRQs in the handler - Show the GPIO base calculation explicitly
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Wan Jiabing authored
linux/io.h has been included at line 6, so remove the duplicate include at line 18. Signed-off-by:
Wan Jiabing <wanjiabing@vivo.com> Reviewed-by:
Damien Le Moal <damien.lemoal@wdc.com> Link: https://lore.kernel.org/r/20210323013727.135571-1-wanjiabing@vivo.comSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Álvaro Fernández Rojas authored
Add a pincontrol driver for BCM6318. BCM6318 allows muxing most GPIOs to different functions. BCM6318 is similar to BCM6328 with the addition of a pad register, and the GPIO meaning of the mux register changes based on the GPIO number. Co-developed-by:
Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by:
Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210324081923.20379-23-noltari@gmail.comSigned-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM6318 SoCs. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210324081923.20379-22-noltari@gmail.comSigned-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in BCM6318 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a pincontrol driver for BCM63268. BCM63268 allows muxing GPIOs to different functions. Depending on the mux, these are either single pin configurations or whole pin groups. Co-developed-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM63268 SoCs. Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in the BCM63268 family SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a pincontrol driver for BCM6368. BCM6368 allows muxing the first 32 GPIOs onto alternative functions. Not all are documented. Co-developed-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM6368 SoCs. Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in BCM6368 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a pincotrol driver for BCM6362. BCM6362 allows muxing individual GPIO pins to the LED controller, to be available by the integrated wifi, or other functions. It also supports overlay groups, of which only NAND is documented. Co-developed-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM6362 SoCs. Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in BCM6362 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a pincotrol driver for BCM6358. BCM6358 allow overlaying different functions onto the GPIO pins. It does not support configuring individual pins but only whole groups. These groups may overlap, and still require the directions to be set correctly in the GPIO register. In addition the functions register controls other, not directly mux related functions. Co-developed-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM6358 SoCs. Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in BCM6358 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a pincontrol driver for BCM6328. BCM6328 supports muxing 32 pins as GPIOs, as LEDs for the integrated LED controller, or various other functions. Its pincontrol mux registers also control other aspects, like switching the second USB port between host and device mode. Co-developed-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM6328 SoCs. Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in BCM6328 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a helper for registering BCM63XX pin controllers. Co-developed-by:
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Álvaro Fernández Rojas authored
Convert existing BCM6345 GPIO binding documentation to YAML and add binding documentation for the GPIO controller found in BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
This is needed for properly registering GPIO regmap as a child of a regmap pin controller. Signed-off-by:
Michael Walle <michael@walle.cc> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by:
Bartosz Golaszewski <bgolaszewski@baylibre.com> Link: https://lore.kernel.org/r/20210324081923.20379-3-noltari@gmail.comSigned-off-by:
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Álvaro Fernández Rojas authored
The current code doesn't check if GPIOLIB_IRQCHIP is enabled, which results in a compilation error when trying to build gpio-regmap if CONFIG_GPIOLIB_IRQCHIP isn't enabled. Fixes: 6a45b0e2 ("gpiolib: Introduce gpiochip_irqchip_add_domain()") Suggested-by:
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- 25 Mar, 2021 7 commits
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Andy Shevchenko authored
In IRQ handler interrupts are already disabled, hence no need to repeat it. Even in the threaded case, which is disabled here, it is not a problem because IRQ framework serializes descriptor handling. Remove disabling IRQ part in the handler. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com>
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Geert Uytterhoeven authored
The Rockchip GPIO and pin control modules are only present on Rockchip SoCs. Hence add a dependency on ARCH_ROCKCHIP, to prevent asking the user about this driver when configuring a kernel without Rockchip platform support. Note that before, the PINCTRL_ROCKCHIP symbol was not visible, and automatically selected when needed. By making it tristate and user-selectable, it became visible for everyone. Fixes: be786ac5 ("pinctrl: rockchip: make driver be tristate module") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20210316134059.2377081-1-geert+renesas@glider.beSigned-off-by:
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Zhiyong Tao authored
When multiple threads operate on the same register resource which include multiple pin, It will make the register resource wrong to control. So we add lock to avoid the case. Signed-off-by:
Zhiyong Tao <zhiyong.tao@mediatek.com> Link: https://lore.kernel.org/r/20210321033150.15380-2-zhiyong.tao@mediatek.comSigned-off-by:
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.13 - Add pin groups for the green and high8 subsets of the Video IN (VIN) pins on R-Car H3 ES2.0+, R-Car M3-W/M3-W+, R-Car M3-N, and R-Car E3.
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Hanna Hawa authored
A System Error (SError, followed by kernel panic) was detected when trying to print the supported pins in a pinctrl device which supports multiple pins per register. This change fixes the pcs_pin_dbg_show() in pinctrl-single driver when bits_per_mux is not zero. In addition move offset calculation and pin offset in register to common function. Fixes: 4e7e8017 ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules") Signed-off-by:
Hanna Hawa <hhhawa@amazon.com> Reviewed-by:
Tony Lindgren <tony@atomide.com> Reviewed-by:
Drew Fustini <drew@beagleboard.org> Link: https://lore.kernel.org/r/20210319152133.28705-4-hhhawa@amazon.comSigned-off-by:
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Hanna Hawa authored
Remove unused parameter 'pin_pos' from pcs_add_pin(). Signed-off-by:
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Hanna Hawa authored
Remove unused parameter 'num_pins_in_register' from pcs_allocate_pin_table(). Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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- 15 Mar, 2021 8 commits
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Shawn Guo authored
It adds ACPI probe support for pinctrl-sc8180x driver. We have one problem with ACPI table, i.e. GIO0 (TLMM) block has one single memory resource to cover 3 tiles defined by SC8180X. To follow the hardware layout of 3 tiles which is already supported DT probe, it adds one function to replace the original single memory resource with 3 named ones for tiles. With that, We can map memory for ACPI in the same way as DT. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
Andy Shevchenko <andriy.shevchenko@intel.com> Link: https://lore.kernel.org/r/20210311024102.15450-1-shawn.guo@linaro.orgSigned-off-by:
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Lina Iyer authored
GPIOs that can be configured as wakeup sources, have their interrupt lines routed to PDC interrupt controller. Provide the interrupt map of the GPIO to its wakeup capable interrupt parent. Signed-off-by:
Lina Iyer <ilina@codeaurora.org> Signed-off-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312034218.3324410-1-bjorn.andersson@linaro.orgSigned-off-by:
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Michal Simek authored
Static analyzer tool found that the ret variable is not initialized but code expects ret value >=0 when pinconf is skipped in the first pinmux loop. The same expectation is for pinmux in a pinconf loop. That's why initialize ret to 0 to avoid uninitialized ret value in first loop or reusing ret value from first loop in second. Addresses-Coverity: ("Uninitialized variables") Signed-off-by:Michal Simek <michal.simek@xilinx.com> Cc: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/e5203bae68eb94b4b8b4e67e5e7b4d86bb989724.1615534291.git.michal.simek@xilinx.comSigned-off-by:
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Jia-Ju Bai authored
When ti_iodelay_pinconf_init_dev() fails, no error return code of ti_iodelay_probe() is assigned. To fix this bug, ret is assigned with the return value of ti_iodelay_pinconf_init_dev(), and then ret is checked. Reported-by:
TOTE Robot <oslab@tsinghua.edu.cn> Signed-off-by:
Jia-Ju Bai <baijiaju1990@gmail.com> Link: https://lore.kernel.org/r/20210306125122.15043-1-baijiaju1990@gmail.comSigned-off-by:
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Jianqun Xu authored
Make pinctrl-rockchip driver to be tristate module, support to build as a module, this is useful for GKI. Reviewed-by:
Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210305003907.1692515-3-jay.xu@rock-chips.comSigned-off-by:
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Jianqun Xu authored
Prepare to make pinctrl driver of rockchip to be module able, this patch remove the select of PINCTRL_ROCKCHIP from ARCH_ROCKCHIP. Signed-off-by:
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Jianqun Xu authored
Module driver may use irq_gc_set_wake. Signed-off-by:
Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210305080658.2422114-1-jay.xu@rock-chips.comSigned-off-by:
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Michal Simek authored
Right now the handling order depends on how entries are coming which is corresponding with order in DT. We have reached the case with DT overlays where conf and mux descriptions are exchanged which ends up in sequence that firmware has been asked to perform configuration before requesting the pin. The patch is enforcing the order that pin is requested all the time first followed by pin configuration. This change will ensure that firmware gets requests in the right order. Signed-off-by:
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