- 04 Oct, 2016 40 commits
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Matt Redfearn authored
For the MIPS remote processor implementation, we need additional IPIs to talk to the remote processor. Since MIPS GIC reserves exactly the right number of IPI IRQs required by Linux for the number of VPs in the system, this is not possible without releasing some recources. This commit introduces mips_smp_ipi_allocate() which allocates IPIs to a given cpumask. It is called as normal with the cpu_possible_mask at bootup to initialise IPIs to all CPUs. mips_smp_ipi_free() may then be used to free IPIs to a subset of those CPUs so that their hardware resources can be reused. Signed-off-by:
Matt Redfearn <matt.redfearn@imgtec.com> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Ohad Ben-Cohen <ohad@wizery.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Lisa Parratt <Lisa.Parratt@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Qais Yousef <qsyousef@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-remoteproc@vger.kernel.org Cc: lisa.parratt@imgtec.com Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14285/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Matt Redfearn authored
When adding a wired entry to the TLB via add_wired_entry, the tlb is flushed with local_flush_tlb_all, which on CPUs with TLBINV results in the new wired entry being flushed again. Behavior of the TLBINV instruction applies to all applicable TLB entries and is unaffected by the setting of the Wired register. Therefore if the TLB has any wired entries, fall back to iterating over the entries rather than blasting them all using TLBINVF. Signed-off-by:
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James Hogan authored
flush_icache_range() flushes icache lines in a protected fashion for kernel addresses, however this isn't correct with EVA where protected cache ops only operate on user addresses, making flush_icache_range() ineffective. Split the implementations of __flush_icache_user_range() from flush_icache_range(), changing the normal flush_icache_range() to use unprotected normal cache ops. Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14156/Signed-off-by:
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James Hogan authored
Convert KVM dynamic translation of guest instructions to flush icache for guest mapped addresses using the new __local_flush_icache_user_range() API to allow the more generic flush_icache_range() to be changed to work on kernel addresses only. Signed-off-by:
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James Hogan authored
Update arch_uprobe_copy_ixol() to use the kmap_atomic() based kernel address to flush the icache with flush_icache_range(), rather than the user mapping. We have the kernel mapping available anyway and this avoids having to switch to using the new __flush_icache_user_range() for the sake of Enhanced Virtual Addressing (EVA) where flush_icache_range() will become ineffective on user addresses. Signed-off-by:
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James Hogan authored
The cacheflush(2) system call uses flush_icache_range() to flush a range of usermode addresses from the icache, so change it to utilise the new __flush_icache_user_range() API to allow the more generic flush_icache_range() to be changed to work on kernel addresses only. Signed-off-by:
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James Hogan authored
flush_icache_range() is used for both user addresses (i.e. cacheflush(2)), and kernel addresses (as the API documentation describes). This isn't really suitable however for Enhanced Virtual Addressing (EVA) where cache operations on usermode addresses must use a different instruction, and the protected cache ops assume user addresses, making flush_icache_range() ineffective on kernel addresses. Split out a new __flush_icache_user_range() and __local_flush_icache_user_range() for users which actually want to flush usermode addresses (note that flush_icache_user_range() already exists on various architectures but with different arguments). The implementation of flush_icache_range() will be changed in an upcoming commit to use unprotected normal cache ops so as to always work on the kernel mode address space. Signed-off-by:
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James Hogan authored
The EVA conditional bc_wback_inv() at the end of flush_icache_range() to flush the modified code all the way back to RAM was apparently there for debug purposes and to accommodate the Malta EVA configuration which makes use of a physical alias, and didn't use the CP0_EBase.WG (Write Gate) bit to put the exception vector in the same physical alias where the exception vector code is written and is being flushed. Now that CP0_EBase.WG is used, lets drop this flush. Signed-off-by:
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Matt Redfearn authored
On CPUs which support the EBase WG (write gate) flag, the most significant bits of the exception base can be changed. Firmware running on a VP(E) using MIPS rproc may change EBase to point into the user segment where the firmware is located such that it can service interrupts. When control is transferred back to the kernel the EBase must be switched back into the kernel segment, such that the kernel's exception vectors are used. Similarly when vectored interrupts (vint) or vectored external interrupt controllers (veic) are enabled an exception vector is allocated from bootmem, and written to the EBase register. Due to the WG flag being clear, only bits 29:12 will be written. Asside from the rproc case above this is normally fine (as it will usually be a low allocation within the KSeg0 range, however when Enhanced Virtual Addressing (EVA) is enabled the allocation may be outside of the traditional KSeg0/KSeg1 address range, resulting in the wrong EBase being written. Correct both cases (configure_exception_vector() for the boot CPU, and per_cpu_trap_init() for secondary CPUs) to write EBase with the WG flag first if supported. On the Malta EVA configuration, KSeg0 is mapped to physical address 0, and memory is allocated from the KUSeg segment which is mapped to physical address 0x80000000, which physically aliases the RAM at 0. This only worked due to the exception base address aliasing the same underlying RAM that was written to & cache flushed, and due to flush_icache_range() going beyond the call of duty and flushing from the L2 cache too (due to the differing physical addresses). Signed-off-by:
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James Hogan authored
When allocating boot memory for the exception vector when vectored interrupts (vint) or vectored external interrupt controllers (veic) are enabled, try to ensure that the virtual address resides in KSeg0 (and WARN should that not be possible). This will be helpful on MIPS64 cores supporting the CP0_EBase Write Gate (WG) bit once we start using the WG bit to write the full ebase into CP0_EBase, as we ideally need to avoid hitting the architecturally poorly defined exception base for Cache Errors when CP0_EBase is in XKPhys. An exception is made for Enhanced Virtual Addressing (EVA) kernels which allow segments to be rearranged and to become uncached during cache error handling, making it valid for ebase to be elsewhere. Signed-off-by:
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James Hogan authored
When reading the CP0_EBase register containing the WG (write gate) bit, the ebase variable should be set to the full value of the register, i.e. on a 64-bit kernel the full 64-bit width of the register via read_cp0_ebase_64(), and on a 32-bit kernel the full 32-bit width including bits 31:30 which may be writeable. Signed-off-by:
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Matt Redfearn authored
This patch enables the MIPS CPS driver for MIPSr6 CPUs. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Reviewed-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: linux-mips@linux-mips.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14228/Signed-off-by:
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Matt Redfearn authored
All calls to mips_cpc_lock_other should be wrapped in mips_cm_lock_other. This only matters if the system has CM3 and is using cpu idle, since otherwise a) the CPC lock is sufficent for CM < 3 and b) any systems with CM > 3 have not been able to use cpu idle until now. Signed-off-by:
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Matt Redfearn authored
MIPS CM3 changed the management of coherence. Instead of a coherence control register with a bitmask of coherent domains, CM3 simply has a coherence enable register with a single bit to enable coherence of the local core. Support this by clearing and setting this single bit to disable / enable coherence. Signed-off-by:
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Matt Redfearn authored
This patch adds support for CPUs implementing the MIPSr6 ISA to the CPS power management code. Three changes are necessary: 1. In MIPSr6, coupled coherence is necessary when CPUS implement multiple Virtual Processors (VPs). 2. MIPSr6 virtual processors are more like real cores and cannot yield to other VPs on the same core, so drop the MT ASE yield instruction. 3. To halt a MIPSr6 VP, the CPC VP_STOP register is used rather than the MT ASE TCHalt CP0 register. Signed-off-by:
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Matt Redfearn authored
Instead of selecting an implementation or vendor specific sync type for the required sync operations, always use the architecturally mandated sync types which previous patches have put in place. The selection of special sync types is now redundant an can be removed. Signed-off-by:
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Matt Redfearn authored
SYNC type 0 is defined in the MIPS architecture as a completion barrier where all loads/stores in the pipeline before the sync instruction must complete before any loads/stores subsequent to the sync instruction. In places where we require loads / stores be globally completed, use the standard completion sync stype. Signed-off-by:
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Matt Redfearn authored
Since R2 of the MIPS architecture, SYNC(0x10) has been an optional but architecturally defined ordering barrier. If a CPU does not implement it, the arch specifies that it must fall back to SYNC(0). In places where we require that the instruction stream not be reordered, but do not require that loads / stores are gloablly completed, use the defined standard sync stype. Signed-off-by:
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Matt Redfearn authored
Add the definitions of sync stype 0 (global completion barrier) and sync stype 0x10 (local ordering barrier) to barrier.h for use with the sync instruction. These types are defined by the MIPS Instruction Set since R2 of the architecture and are documented in document MD00087 table 6.5. Signed-off-by:
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Matt Redfearn authored
This code makes large use of barriers, which had quite vague descriptions. Update the comments to make the choice of barrier and reason for it more clear. Signed-off-by:
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Matt Redfearn authored
The check for whether a CPU required the FSB flush workaround previously required every CPU not requiring it to be whitelisted. That approach does not scale well as new CPUs are introduced so change the default from a WARN and returning an error to just returning 0. Any CPUs requiring the workaround can then be added to the blacklist. Signed-off-by:
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Matt Redfearn authored
MIPS CM version 3 removed the CPC_CL_OTHER register and instead the CM_CL_OTHER register is used to redirect the CPC_OTHER region. As such, we should not write the unimplmented register and can avoid the spinlock as well. These lock functions should aleady be called within the context of a mips_cm_{lock,unlock}_other pair ensuring the correct CPC_OTHER region will be accessed. Signed-off-by: -
Matt Redfearn authored
Checkpatch complains about use of bare unsigned type. Signed-off-by:
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Aaro Koskinen authored
Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14250/Signed-off-by:
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Aaro Koskinen authored
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Aaro Koskinen authored
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Aaro Koskinen authored
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Aaro Koskinen authored
PHY access through the board helper is impossible with the current drivers, so delete this code. Signed-off-by:
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Aaro Koskinen authored
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Aaro Koskinen authored
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Aaro Koskinen authored
Leave that to actual ethernet/phy drivers. Signed-off-by:
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Aaro Koskinen authored
Delete legacy hack for broken bootloaders. The warning has been in kernel for several years, and if there are still users using such bootloaders, they can fix the boot by supplying a proper DTB. Signed-off-by:
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Masahiro Yamada authored
In many of clk_disable() implementations, it is a no-op for a NULL pointer input, but this is one of the exceptions. Making it treewide consistent will allow clock consumers to call clk_disable() without NULL pointer check. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by:
Florian Fainelli <f.fainelli@gmail.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: bcm-kernel-feedback-list@broadcom.com Cc: linux-arm-kernel@lists.infradead.org Patchwork: https://patchwork.linux-mips.org/patch/14264/Signed-off-by:
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Keith Busch authored
This patch removes creating a fake pci device in MIPS early config access and instead just uses the pci bus to get the same functionality. The struct pci_dev is too large to allocate on the stack, and was relying on compiler optimizations to remove its usage. Signed-off-by:
Keith Busch <keith.busch@intel.com> Reviewed-by:
Atsushi Nemoto <anemo@mba.ocn.ne.jp> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14253/Signed-off-by:
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Geert Uytterhoeven authored
Replace the custom minimal clock implementation for Toshiba TXx9 by a basic implementation using the Common Clock Framework. The only clocks that are provided are those needed by TXx9-specific drivers ("imbus" and "spi" (TX4938 only)), and their common parent clock "gbus". Other clocks can be added when needed. Signed-off-by:Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Reviewed-by:
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Geert Uytterhoeven authored
While the custom minimal TXx9 clock implementation doesn't need or use clock (un)prepare calls (they are dummies if !CONFIG_HAVE_CLK_PREPARE), they are mandatory when using the Common Clock Framework. Hence add them, to prepare for the advent of CCF. Signed-off-by:
Guenter Roeck <linux@roeck-us.net> Cc: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Cc: Wim Van Sebroeck <wim@iguana.be> Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14238/Signed-off-by:
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Geert Uytterhoeven authored
txx9_gpio_init() calls gpiochip_add_data(), which fails with -ENOMEM as it is called too early in the boot process. This causes all subsequent GPIO operations to fail silently (before commit 54d77198 ("gpio: bail out silently on NULL descriptors") it printed the error message "gpiod_direction_output_raw: invalid GPIO" on RBTX49[23]7). Postpone all GPIO setup to .arch_init() time to fix this. Suggested-by:
Linus Walleij <linus.walleij@linaro.org> Cc: linux-mips@linux-mips.org Cc: linux-gpio@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14237/Signed-off-by:
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Geert Uytterhoeven authored
txx9_gpio_init() calls gpiochip_add_data(), which fails with -ENOMEM as it is called too early in the boot process. This causes all subsequent GPIO operations to fail silently. Postpone all GPIO setup to .arch_init() time to fix this. Suggested-by:
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Masahiro Yamada authored
Remove unneeded variables and assignments. Signed-off-by:
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Yang Ling authored
The patch adds RTC support for Loongson1C board, and enable the external crystal when the RTC is first powered up. Signed-off-by:
Yang Ling <gnaygnil@gmail.com> Cc: keguang.zhang@gmail.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14214/Signed-off-by:
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