- 10 May, 2021 40 commits
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Dennis Li authored
For aldebaran, hardware will not clear error status automatically when reading error status register, insteadly driver should set clear bit of the error status register explicitly to clear error status. Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Dennis Li authored
The bit 11 of GCEA_ERR_STATUS register is used to clear GCEA error status. Signed-off-by:
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Aric Cyr authored
- adding missed FW promotion Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Stylon Wang <stylon.wang@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Anthony Koo authored
- Implement INBOX0 messaging for HW lock Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Dmytro Laktyushkin authored
Right now the flag simply selects memory config 0 when flag is true however 420 modes benefit more from memory config 3. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Anthony Wang authored
[Why] In some pipe harvesting configs, we will select the incorrect dpp_inst when programming DTO. This is because when any intermediate pipe is fused, resource instances are no longer in 1:1 correspondence with pipe index. [How] When looping through pipes to program DTO, get the dpp_inst associated with each pipe from res_pool. Signed-off-by:
Anthony Wang <anthony1.wang@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Ilya Bakoulin authored
[Why] Some DSC tests fail because stream pixel encoding does not change its value according to the type requested in the DPCD test params. [How] Set stream pixel encoding before updating DSC config and configuring the test pattern. Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
Hanghong Ma <Hanghong.Ma@amd.com> Acked-by:
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Ilya Bakoulin authored
[Why] Currently, the code that fills the clock table can miss filling information about some of the higher voltage states advertised by the SMU. This, in turn, may cause some of the higher pixel clock modes (e.g. 8k60) to fail validation. [How] Fill the table with one entry per DCFCLK level instead of one entry per FCLK level. This is needed because the maximum FCLK does not necessarily need maximum voltage, whereas DCFCLK values from SMU cover the full voltage range. Signed-off-by:
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Wenjing Liu authored
[how] The change includes some dp link training refactors: 1. break down is_ch_eq_done to checking individual conditions in its own function. 2. update dpcd_set_training_pattern to take in dc_dp_training_pattern as input. 3. moving lttpr mode struct definition into link_service_types.h Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
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Chaitanya Dhere authored
[Why] DETBufferSizeInKByte is not expected to be sub-dividable, hence unsigned int is a better suited data-type. Change it to an array as well to satisfy current requirements. [How] Change the data-type of DETBufferSizeInKByte to an unsigned int array. Modify the all the variables like DETBufferSizeY, DETBufferSizeC that are involved in DETBufferSizeInKByte calculations to unsigned int in all the display_mode_vba_xx files. Signed-off-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Reviewed-by:
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Fangzhi Zuo authored
Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Mikita Lipski <Mikita.Lipski@amd.com> Acked-by:
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Jimmy Kizito authored
[Why & How] Add functionality useful for DP link training to public interface. Signed-off-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Jimmy Kizito authored
[Why] When enabling a DisplayPort stream: - Optionally reducing link bandwidth between failed link training attempts should progressively relax training requirements. - Abandoning link training altogether if a sink is unplugged should avoid unnecessary training attempts. [How] - Add fallback parameter to DP link training function and reduce link bandwidth between failed training attempts as long as stream bandwidth requirements are met. - Add training status for sink unplug and abort training when this status is reported. Signed-off-by:
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Jimmy Kizito authored
[Why] Some links are dynamically assigned link encoders on stream enablement. [How] Update DisplayPort training parameter determination stage that assumes link encoder statically assigned to link. Signed-off-by:
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Jimmy Kizito authored
[Why] Some extra provisions are required during DPRX detection for links which lack physical HPD and AUX/DDC pins. [How] Avoid attempting to access nonexistent physical pins during DPRX detection. Signed-off-by:
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Dennis Li authored
The original codes use ras status and kernl errno together in the same function, which is a wrong code style. Signed-off-by:
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Zhan Liu authored
[Why] If GPU is in reset state, force enabling link will cause unexpected behaviour. [How] Avoid handling HPD IRQ when GPU is in reset state. Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
Nikola Cornij <nikola.cornij@amd.com> Signed-off-by:
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Oak Zeng authored
If RAS is disabled through amdgpu_ras_enable kernel parameter, we should quit the RAS initialization eariler to avoid initialization of some RAS data structure such as sysfs etc. Reviewed-by:
Oak Zeng <Oak.Zeng@amd.com> Signed-off-by:
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Philip Yang authored
If migration copy failed because process is killed, or out of VRAM or system memory, pass error code back to caller to handle error gracefully. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Luben Tuikov authored
Export the runtime-set "ras_hw_enabled" and "ras_enabled" to debugfs, for debugging. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
John Clements <John.Clements@amd.com> Signed-off-by:
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Luben Tuikov authored
Rename, ras_hw_supported --> ras_hw_enabled, and ras_features --> ras_enabled, to show that ras_enabled is a subset of ras_hw_enabled, which itself is a subset of the ASIC capability. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Luben Tuikov authored
Move ras_hw_supported into struct amdgpu_dev. The dependency is: struct amdgpu_ras <== struct amdgpu_dev <== ASIC, read as "struct amdgpu_ras depends on struct amdgpu_dev, which depends on the hardware." This can be loosely understood as, "if RAS is supported, which is property of the ASIC (struct amdgpu_dev), then we can access struct amdgpu_ras." v2: Fix a typo: must binary AND in ternary cond in amdgpu_ras.c Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: -
Luben Tuikov authored
Remove redundant ras->supported, as this value is also stored in adev->ras_features. Use adev->ras_features, as that supercedes "ras", since the latter is its member. The dependency goes like this: ras <== adev->ras_features <== hw_supported, and is read as "ras depends on ras_features, which depends on hw_supported." The arrows show the flow of information, i.e. the dependency update. "hw_supported" should also live in "adev". Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Sathishkumar S authored
update suspend register settings in Non-DPG mode. Signed-off-by:
Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Dennis Li authored
Add shader codes to explicitly clear specific SGPRs, such as flat_scratch_lo, flat_scratch_hi and so on. And also correct the allocation size of SGPRs in PGM_RSRC1. Signed-off-by:
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Mukul Joshi authored
Enable TCP channel hashing to match DF hash settings for Aldebaran. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Signed-off-by:
Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Eric Huang authored
In NPS4 BIOS we need to find the closest numa node when creating topology io link between cpu and gpu, if PCI driver doesn't set it. Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Reviewed-by:
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Alex Deucher authored
Vangogh follows other APUs, but also allows core clock adjustments. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
APUs only support adjusting the SCLK domain. Reviewed-by:
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Evan Quan authored
Available with 68.18.0 and later PMFWs. Signed-off-by:
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Evan Quan authored
Supported by some latest ASICs. Signed-off-by:
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Bas Nieuwenhuizen authored
The builtin size check isn't really the right thing for AMD modifiers due to a couple of reasons: 1) In the format structs we don't do set any of the tilesize / blocks etc. to avoid having format arrays per modifier/GPU 2) The pitch on the main plane is pixel_pitch * bytes_per_pixel even for tiled ... 3) The pitch for the DCC planes is really the pixel pitch of the main surface that would be covered by it ... Note that we only handle GFX9+ case but we do this after converting the implicit modifier to an explicit modifier, so on GFX9+ all framebuffers should be checked here. There is a TODO about DCC alignment, but it isn't worse than before and I'd need to dig a bunch into the specifics. Getting this out in a reasonable timeframe to make sure it gets the appropriate testing seemed more important. Finally as I've found that debugging addfb2 failures is a pita I was generous adding explicit error messages to every failure case. Fixes: f258907f ("drm/amdgpu: Verify bo size can fit framebuffer size on init.") Tested-by:
Simon Ser <contact@emersion.fr> Signed-off-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
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Bas Nieuwenhuizen authored
Otherwise tiling modes that require the values form this field (In particular _*_X) would be corrupted upon video decode. Copied from the VCN v2 code. Fixes: 99541f39 ("drm/amdgpu: add mc resume DPG mode for VCN3.0") Reviewed-and-Tested by: Leo Liu <leo.liu@amd.com> Signed-off-by:
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Alex Deucher authored
Change to 60s. This matches what we already do in virtualization. Infinite timeout can lead to deadlocks in the kernel. Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Sathishkumar S authored
enable vcn mgcg flag for picasso. Signed-off-by:
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Mike Li authored
The L1 cache information has been updated and the L2/L3 information has been added. The changes have been made for Vega10 and newer ASICs. There are no changes for the older ASICs before Vega10. Signed-off-by:
Mike Li <Tianxinmike.Li@amd.com> Signed-off-by:
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Fabio M. De Francesco authored
drm_modeset_lock_all() is not needed here, so it is replaced with drm_modeset_lock(). The crtc list around which we are looping never changes, therefore the only lock we need is to protect access to crtc->state. Suggested-by:
Daniel Vetter <daniel@ffwll.ch> Suggested-by:
Matthew Wilcox <willy@infradead.org> Signed-off-by:
Fabio M. De Francesco <fmdefrancesco@gmail.com> Reviewed-by:
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Tom Rix authored
Static analysis reports this problem amdgpu_pm.c:478:16: warning: The right operand of '<' is a garbage value for (i = 0; i < data.nums; i++) { ^ ~~~~~~~~~ In some cases data is not set. Initialize to 0 and flag not setting data as an error with the existing check. Signed-off-by:Tom Rix <trix@redhat.com> Signed-off-by:
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Kees Cook authored
Avoid leaving a hanging pre-allocated clock_info if last mode is invalid, and avoid heap corruption if no valid modes are found. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=211537 Fixes: 6991b8f2 ("drm/radeon/kms: fix segfault in pm rework") Signed-off-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
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