- 07 Nov, 2023 19 commits
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Anthony Koo authored
- Increase number of bits for IPS boot option Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Aric Cyr authored
This version brings along following fixes: Update test link rate DPCD bit field to match spec Enable RCO options for dcn35 Add missing dml2 init value for dcn35 Enable DCN clock gating DCN35 Disable cm power optimization Allow 16 max_slices for DP2 DSC Fix OTG disable workaround logic Enable more IPS options Fix FRL assertion on boot Fix missing blendTF programming Update DP HPO MSA with colorimetry from test request Fix handling duplicate planes on one stream Acked-by:
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Roman Li authored
[Why] For lighting up, some dml2 params needs to be initialized. One of them escaped initial patch under: "drm/amd/display: Add DCN35 DML2 support" [How] Add missing initialization. Fixes: 115009d1 ("drm/amd/display: Add DCN35 DML2 support") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Roman Li <roman.li@amd.com> Tested-by:
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Taimur Hassan authored
[Why] DENTIST was hanging when performing DISPCLK update with OTG enabled, as OTG disable workaround was not executing. [How] Workaround was checking against current_state before running, but when called from optimize_bandwidth (safe_to_lower), we should be checking against context instead. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Taimur Hassan <syed.hassan@amd.com> Tested-by:
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ChunTao Tso authored
[Why] For Replay, if we receive HPD, it doesn’t need to reboot the display. We don’t need to return anything exactly. [How] Return nothing just because we don’t need to reboot the display. Signed-off-by:
ChunTao Tso <chuntao.tso@amd.com> Acked-by:
Jerry Zuo <jerry.zuo@amd.com> Tested-by:
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Dennis Chan authored
[why] It's useful to disable the recovery mechanism when debugging replay desync errors. Signed-off-by:
Dennis Chan <Dennis.Chan@amd.com> Acked-by:
Robin Chen <robin.chen@amd.com> Tested-by:
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Yihan Zhu authored
[WHY & HOW] Enabling SCE after boot up will cause color distortion. Reviewed-by:
Ovidiu Bunea <ovidiu.bunea@amd.com> Acked-by:
Yihan Zhu <yihan.zhu@amd.com> Tested-by:
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George Shen authored
[Why] Some DP link layer tests request a different colorimetry than the default one that is used. Currently, our test automation logic does not update the MSA with the test request value for DP HPO case. [How] Update HPO MSA colorimetry with test automation request value. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
George Shen <george.shen@amd.com> Tested-by:
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George Shen authored
[Why] An SCR was made to the DP2.0 spec that updated the bit field definition for UHBR13.5 in the test link rate DPCD register. [How] Add new translation to match the SCR update. Keep old translation for backwards compatibility. Reviewed-by:
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Fangzhi Zuo authored
Enable 12 and 16 max_slices for DP2 DSC Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
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Sung Joon Kim authored
[why] To help isolate static screen and video playback tests, we want to enable an IPS option to allow IPS only on D3 cycle. [how] Add DISABLE_DYNAMIC and DISABLE_ALL IPS disable flags for user control. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Sung Joon Kim <sungkim@amd.com> Tested-by:
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Daniel Miess authored
[Why & How] Enable root clock optimization options for dcn35 for power savings Reviewed-by:
Daniel Miess <daniel.miess@amd.com> Tested-by:
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Sung Joon Kim authored
[why] Make sure to ungate the clocks on boot so programming sequence is done successfully. [how] Move the ungate logic after bios init. Reviewed-by:
Xi (Alex) Liu <xi.liu@amd.com> Acked-by:
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Ilya Bakoulin authored
[Why] When MPO surface pixel format is not ARGB8888, fast update can miss programming blendTF. [How] Set the gamma_change update flag on blend_tf change. Reviewed-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by:
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Aric Cyr authored
This version brings along following fixes: On boot disable domain22 force power on decouple dmcub execution to reduce lock granularity Enable fast update on blendTF change Fix blend LUT programming Program plane color setting correctly amend HPD handler for Replay Avoid NULL dereference of timing generator Acked-by:
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JinZe.Xu authored
[Why] On some systems dmub commands run at high IRQ, so long running commands will block other interrupts. [How] Decouple wait_for_idle from dmcub queue/execute/wait. Reviewed-by:
Josip Pavic <josip.pavic@amd.com> Acked-by:
JinZe.Xu <jinze.xu@amd.com> Tested-by:
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Anthony Koo authored
- Minor formatting changes - Update defines to match the bit width of the field it is used for - Add new boot up bits to control HW sub block regions power down Reviewed-by:
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Daniel Miess authored
[Why] HDCP2 enablement fails when domain22 is set to force power on [How] Disable force power on for domain22 on startup Reviewed-by:
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Surbhi Kakarya authored
The purpose of this patch is to disable XNACK or set XNACK OFF mode on SRIOV platform which doesn't support it. This will prevent user-space application to fail or result into unexpected behaviour whenever the application need to run test-case in XNACK ON mode. Signed-off-by:
Surbhi Kakarya <surbhi.kakarya@amd.com> Reviewed-by:
Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by:
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- 06 Nov, 2023 2 commits
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https://gitlab.freedesktop.org/agd5f/linuxDave Airlie authored
amd-drm-next-6.7-2023-11-03: amdgpu: - Fix RAS support check - RAS fixes - MES fixes - SMU13 fixes - Contiguous memory allocation fix - BACO fixes - GPU reset fixes - Min power limit fixes - GFX11 fixes - USB4/TB hotplug fixes - ARM regression fix - GFX9.4.3 fixes - KASAN/KCSAN stack size check fixes - SR-IOV fixes - SMU14 fixes - PSP13 fixes - Display blend fixes - Flexible array size fixes amdkfd: - GPUVM fix radeon: - Flexible array size fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231103173203.4912-1-alexander.deucher@amd.com
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2023-11-02' of git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next-fixes for v6.7-rc1: - dt binding fix for ssd132x - Initialize ssd130x crtc_state to NULL. Signed-off-by:
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- 03 Nov, 2023 19 commits
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Ilya Bakoulin authored
[Why] Full update is not required on surface blend TF change. [How] Update full_update_required condition. Reviewed-by:
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Ilya Bakoulin authored
[Why] LUT write index does not get reset to zero when writing the LUT values for each separate RGB component, which results in wrong data for 2 of the 3 components. [How] Reset LUT write index to zero before writing each component's data. Reviewed-by:
Krunoslav Kovac <krunoslav.kovac@amd.com> Acked-by:
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Sung Joon Kim authored
[why] There are some registers for plane color that are skipped programming on resume. Need to add those as part of the sequence. [how] Add new function hook for programming plane color control. Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Acked-by:
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Hawking Zhang authored
Query boot status and report boot errors. A follow up change is needed to stop GPU initialization if boot fails. v2: only invoke the call for dGPU (Le/Lijo) Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Le Ma <le.ma@amd.com> Signed-off-by:
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Hawking Zhang authored
Add psp v13 function to query boot status. v2: limit the use case to dGPU only (Lijo) Signed-off-by:
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Li Ma authored
dorp fw version check and using max table size to init table. Signed-off-by:
Li Ma <li.ma@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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Li Ma authored
Update driver if headers and metrics table in smu v14_0_0 after smu fw promotion. Drop the legacy metrics table and add warning of checking pmfw version. Signed-off-by:
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Hawking Zhang authored
Add MP0_C2PMSG_109/126 register field shift/masks that are used to identify boot status by driver. Signed-off-by:
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Ma Jun authored
Use a new struct array to define the asic information which asic type needs to be fixed. Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Tim Huang authored
Use a proper MEID to make sure the CP_HQD_* and CP_GFX_HQD_* registers can be touched when initialize the compute and gfx mqd in mes_self_test. Otherwise, we expect no response from CP and an GRBM eventual timeout. Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Acked-by:
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Tao Zhou authored
Handle xgmi hive case. Suggested-by:
Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by:
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Ma Jun authored
The current code checks sriov vf flag multiple times when creating hwmon sysfs. So fix it. Signed-off-by:
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Felix Kuehling authored
Instead of attaching the eviction fence when a KFD BO is first mapped, attach it when it is allocated or imported. This in preparation to allow KFD BOs to be mapped using the render node API. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Felix Kuehling authored
Let amdgpu_vm_handle_moved update all BO VA mappings of BOs reserved by the caller. This will be useful for handling extra BO VA mappings in KFD VMs that are managed through the render node API. v2: rebase against drm_exec changes (Alex) Signed-off-by:
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Nathan Chancellor authored
When building ARCH=x86_64 allmodconfig with clang, which will typically have sanitizers enabled, there is a warning about a large stack frame. drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/display_mode_core.c:6265:13: error: stack frame size (2520) exceeds limit (2048) in 'dml_prefetch_check' [-Werror,-Wframe-larger-than] 6265 | static void dml_prefetch_check(struct display_mode_lib_st *mode_lib) | ^ 1 error generated. Notably, GCC 13.2.0 does not do too much of a better job, as it is right at the current limit of 2048 (and others have reported being over with older GCC versions): drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/display_mode_core.c: In function 'dml_prefetch_check': drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/display_mode_core.c:6705:1: error: the frame size of 2048 bytes is larger than 1800 bytes [-Werror=frame-larger-than=] 6705 | } | ^ In the past, these warnings have been avoided by reducing the number of parameters to various functions so that not as many arguments need to be passed on the stack. However, these patches take a good amount of effort to write despite being mechanical due to code structure and complexity and they are never carried forward to new generations of the code so that effort has to be expended every new hardware generation, which becomes harder to justify as time goes on. To avoid having a noticeable or lengthy breakage in all{mod,yes}config, which are easy testing targets that have -Werror enabled, increase the limit for configurations that have KASAN or KCSAN enabled by 50% so that cases of extremely poor code generation can still be caught while not breaking the majority of builds. CONFIG_KMSAN also causes high stack usage but the frame limit is already set to zero when it is enabled, which is accounted for by the check for CONFIG_FRAME_WARN=0 in the dml2 Makefile. Signed-off-by:Nathan Chancellor <nathan@kernel.org> Signed-off-by:
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Wayne Lin authored
[Why & How] Check whether assigned timing generator is NULL or not before accessing its funcs to prevent NULL dereference. Reviewed-by:
Wayne Lin <wayne.lin@amd.com> Tested-by:
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Mukul Joshi authored
Update cache info reporting based on compute and memory partitioning modes. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
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Mukul Joshi authored
GFX 9.4.3 uses a new version of the GC info table which contains the cache info. This patch adds a new function to populate the cache info from IP discovery for GFX 9.4.3. Signed-off-by:
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Alex Deucher authored
Issues were reported with commit 1cfb4d61 ("drm/amdgpu: put MQDs in VRAM") on an ADLINK Ampere Altra Developer Platform (AVA developer platform). Various ARM systems seem to have problems related to PCIe and MMIO access. In this case, I'm not sure if this is specific to the ADLINK platform or ARM in general. Seems to be some coherency issue with VRAM. For now, just don't put MQDs in VRAM on ARM. Link: https://lists.freedesktop.org/archives/amd-gfx/2023-October/100453.html Fixes: 1cfb4d61 ("drm/amdgpu: put MQDs in VRAM") Acked-by:
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