1. 04 Oct, 2023 9 commits
  2. 03 Oct, 2023 2 commits
  3. 02 Oct, 2023 5 commits
  4. 29 Sep, 2023 21 commits
  5. 28 Sep, 2023 3 commits
    • Dave Airlie's avatar
      Merge tag 'drm-misc-next-2023-09-27' of git://anongit.freedesktop.org/drm/drm-misc into drm-next · 79fb229b
      Dave Airlie authored
      drm-misc-next for v6.7-rc1:
      
      UAPI Changes:
      - drm_file owner is now updated during use, in the case of a drm fd
        opened by the display server for a client, the correct owner is
        displayed.
      - Qaic gains support for the QAIC_DETACH_SLICE_BO ioctl to allow bo
        recycling.
      
      Cross-subsystem Changes:
      - Disable boot logo for au1200fb, mmpfb and unexport logo helpers.
        Only fbcon should manage display of logo.
      - Update freescale in MAINTAINERS.
      - Add some bridge files to bridge in MAINTAINERS.
      - Update gma500 driver repo in MAINTAINERS to point to drm-misc.
      
      Core Changes:
      - Move size computations to drm buddy allocator.
      - Make drm_atomic_helper_shutdown(NULL) a nop.
      - Assorted small fixes in drm_debugfs, DP-MST payload addition error handling.
      - Fix DRM_BRIDGE_ATTACH_NO_CONNECTOR handling.
      - Handle bad (h/v)sync_end in EDID by clipping to htotal.
      - Build GPUVM as a module.
      
      Driver Changes:
      - Simple drivers don't need to cache prepared result.
      - Call drm_atomic_helper_shutdown() in shutdown/unbind for a whole lot
        more drm drivers.
      - Assorted small fixes in amdgpu, ssd130x, bridge/it6621, accel/qaic,
        nouveau, tc358768.
      - Add NV12 for komeda writeback.
      - Add arbitration lost event to synopsis/dw-hdmi-cec.
      - Speed up s/r in nouveau by not restoring some big bo's.
      - Assorted nouveau display rework in preparation for GSP-RM,
        especially related to how the modeset sequence works and
        the DP sequence in relation to link training.
      - Update anx7816 panel.
      - Support NVSYNC and NHSYNC in tegra.
      - Allow multiple power domains in simple driver.
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
      
      From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/f1fae5eb-25b8-192a-9a53-215e1184ce81@linux.intel.com
      79fb229b
    • Imre Deak's avatar
      drm/i915/fdi: Recompute state for affected CRTCs on FDI links · f67ff36f
      Imre Deak authored
      Recompute the state of all CRTCs on an FDI link during a modeset that
      may be affected by the modeset of other CRTCs on the same link. This
      ensures that each CRTC on the link maximizes its BW use (after another
      CRTC is disabled).
      
      In practice this means recomputing pipe B's config on IVB if pipe C gets
      disabled.
      
      v2:
      - Add the change recomputing affected CRTC states in a separate patch.
        (Ville)
      v3: (Ville)
      - Constify old and new crtc states.
      - Check for fused off pipe C.
      - Fix new vs. old crtc state mixup.
      - Drop check for pipe C's enabled state.
      
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-12-imre.deak@intel.com
      f67ff36f
    • Imre Deak's avatar
      drm/i915/fdi: Improve FDI BW sharing between pipe B and C · 998d2cd3
      Imre Deak authored
      At the moment modesetting pipe C on IVB will fail if pipe B uses 4 FDI
      lanes. Make the BW sharing more dynamic by trying to reduce pipe B's
      link bpp in this case, until pipe B uses only up to 2 FDI lanes.
      
      For this instead of the encoder compute config retry loop - which
      reduced link bpp only for the encoder's pipe - reduce the maximum link
      bpp for pipe B/C as required after all CRTC states are computed and
      recompute the CRTC states with the new bpp limit.
      
      Atm, all FDI encoder's compute config function returns an error if a BW
      constrain prevents increasing the pipe bpp value. The corresponding
      crtc_state->bw_constrained check can be replaced with checking
      crtc_state->max_link_bpp_x16, add TODO comments for this. SDVO is an
      exception where this case is only handled in the outer config retry
      loop, failing the modeset with a WARN, add a FIXME comment to handle
      this in the encoder code similarly to other encoders.
      
      v2:
      - Don't assume that a CRTC is already in the atomic state, while
        reducing its link bpp.
      - Add DocBook description to intel_fdi_atomic_check_link().
      v3:
      - Enable BW management for FDI links in a separate patch. (Ville)
      v4: (Ville)
      - Fail the SDVO encoder config computation if it doesn't support the
        link bpp limit.
      - Add TODO: comments about checking link_bpp_x16 instead of
        bw_constrained.
      v5:
      - Replace link bpp limit check with a FIXME: comment in
        intel_sdvo_compute_config(). (Ville)
      
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      [Amended commit message wrt. changes in v5]
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20230921195159.2646027-11-imre.deak@intel.com
      998d2cd3