- 26 Sep, 2017 40 commits
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Harry Wentland authored
Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
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Harry Wentland authored
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Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Harry Wentland authored
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Harry Wentland authored
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Harry Wentland authored
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Zeyu Fan authored
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Zeyu Fan <Zeyu.Fan@amd.com> Reviewed-by:
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Yue Hin Lau authored
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Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
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Charlene Liu authored
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Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Eric Yang authored
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Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Tony Cheng authored
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Eric Yang authored
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Eric Yang authored
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Tony Cheng authored
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Ding Wang authored
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Ding Wang <Ding.Wang@amd.com> Reviewed-by:
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Harry Wentland authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Wesley Chalmers authored
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Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
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Zeyu Fan authored
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Dmytro Laktyushkin authored
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Eric Yang authored
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Tony Cheng authored
still quite hacky. but this address not properly shutdown pipe video underlay + enable another display case, as well as mode changes with video overlay. Signed-off-by:
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Dmytro Laktyushkin authored
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Tony Cheng authored
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Tony Cheng authored
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Tony Cheng authored
remove redundant DPP_CLOCK_ENABLE in ipp. clock programmed by HWSS Signed-off-by:
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Roman Li authored
Fixing 2 bugs in compressor: - array out of bounds due to incorrect index - compressor options always 0 due to union overwrite Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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Wenjing Liu authored
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Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Zeyu Fan authored
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Dmytro Laktyushkin authored
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Harry Wentland authored
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Harry Wentland authored
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Harry Wentland authored
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Leo (Sunpeng) Li authored
In any drm ioctl call, drm_atomic_state_clear() is called at the end to destroy the states; even if atomic check fails. Therefore, releasing states on atomic check failure is incorrect. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Acked-by:
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Eric Yang authored
When we exit MPO, disconnected pipes cannot be immediately powergated because registers are double buffered, and actual disconnection does not happen until VUPDATE. So it is differred for many flips. However in the case of exiting full screen, the transition from MPO to grph only back to MPO is very fast and also involves increasing of watermarks. Since the underlay pipe is never powergated in this scenario, it keeps its old TTU counter, which causes allowPstateSwitch signal to be de-asserted when compared to the new increased watermark. Since the new pipe is not enabled yet, the signal will be continously de-asserted and hangs SMU, who's waiting for the signal to do pstate switching. Signed-off-by:
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Anthony Koo authored
Also need to change default to off Signed-off-by:
Anthony Koo <anthony.koo@amd.com> Reviewed-by:
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Tony Cheng authored
- root cause was we disable opp clk in MPC disconnect - hubp_blank is not double buffered, so we can't blank until MPC disconnect or we have risk of underflow Signed-off-by:
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Charlene Liu authored
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Eric Yang authored
MPCC_OPP_ID must be programmed to 0xf to properly turn off the mpcc. However the software state of the mpcc must keep track of the opp that the mpcc is attached to for reset to properly happen. This is kinda hacky right now, but a good solution may involve a lot of work. Signed-off-by:
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Charlene Liu authored
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