- 19 Jan, 2024 9 commits
-
-
Lucas De Marchi authored
Use DIV_ROUND_UP_ULL() so it also works on 32bit build. Fixes: dd08ebf6 ("drm/xe: Introduce a new DRM driver for Intel GPUs") Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240119001612.2991381-2-lucas.demarchi@intel.com
-
Rodrigo Vivi authored
This information is already present at /sys/kernel/debug/dri/0/gt0/uc/guc_log if needed. v2: add missing chunk v3: remove spurious line Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com>
-
Badal Nilawar authored
Print xe->info.skip_guc_pc in xe info Cc: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by:
Badal Nilawar <badal.nilawar@intel.com> Reviewed-by:
Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240119131025.1872947-1-badal.nilawar@intel.comSigned-off-by:
-
Jani Nikula authored
All of the attributes, as well as the array of attributes, can be const and placed in rodata. Reviewed-by:
Thomas Hellström <thomas.hellstrom@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240117122044.1544174-5-jani.nikula@intel.comSigned-off-by:
Jani Nikula <jani.nikula@intel.com>
-
Jani Nikula authored
Place the function pointers in rodata. Reviewed-by:
-
Jani Nikula authored
Make hwmon_info a const array of const pointers, and let it be placed in rodata. Reviewed-by:
-
Jani Nikula authored
The irq_chip definition can be const, make it so. Reviewed-by:
-
Jani Nikula authored
Place the function pointers in rodata. Also drop the extra declaration while at it. Reviewed-by:
-
Vinod Govindapillai authored
drm_gem_private_object_init expect the object size be page size aligned. The xe_bo create functions do not update the size for any alignment requirements. So align cfb size to be page size aligned in xe stolen memory handling. Signed-off-by:
Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by:
Jouni Högander <jouni.hogander@intel.com> Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240112092803.61664-2-vinod.govindapillai@intel.com
-
- 18 Jan, 2024 9 commits
-
-
Fei Yang authored
In function write_pgtable, the calculation of chunk in the do-while loop is wrong, we should always compare against remaining size instead of the total size update->qwords. Signed-off-by:
Fei Yang <fei.yang@intel.com> Reviewed-by:
-
Daniele Ceraolo Spurio authored
The GSC notifies us of a proxy request via the HECI2 interrupt. The interrupt must be enabled both in the HECI layer and in our usual gt irq programming; for the latter, the interrupt is enabled via the same enable register as the GSC CS, but it does have its own mask register. When the interrupt is received, we also need to de-assert it in both layers. The handling of the proxy request is deferred to the same worker that we use for GSC load. New flags have been added to distinguish between the init case and the proxy interrupt. v2: rename irq define, fix include ordering (Alan) Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by:
Alan Previn <alan.previn.teres.alexis@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240117182621.2653049-3-daniele.ceraolospurio@intel.com
-
Daniele Ceraolo Spurio authored
The GSC uC needs to communicate with the CSME to perform certain operations. Since the GSC can't perform this communication directly on platforms where it is integrated in GT, the graphics driver needs to transfer the messages from GSC to CSME and back. The proxy flow must be manually started after the GSC is loaded to signal to GSC that we're ready to handle its messages and allow it to query its init data from CSME. Note that the component must be removed before the pci_remove call completes, so we can't use a drmm helper for it and we need to instead perform the cleanup as part of the removal flow. v2: add function documentation, more targeted memory clear, clearer logs and variable names (Alan) Signed-off-by:
-
Michal Wajdeczko authored
Add initial documentation for recently updated xe_guc_ct_send_recv(). Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Reviewed-by:
Matthew Brost <matthew.brost@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240112102554.761-2-michal.wajdeczko@intel.com
-
Michal Wajdeczko authored
Most of the synchronous GuC HXG action responses are defined in such a way that only mandatory DATA0 from the HXG header is used and only in few cases it is more than MBZ (must be zero). For those cases where HXG action returns just DATA0, return that value if caller didn't provide buffer for the full response. Signed-off-by:
-
Michal Wajdeczko authored
The mapping between HW IP version and its description is const, so mark it as such. Signed-off-by:
Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240116120207.1133-1-michal.wajdeczko@intel.com
-
Karthik Poosa authored
The GuC handles the WA, the KMD just needs to set the flag to enable it on the appropriate platforms. v2: - Fixed CI checkpatch warning, alignment should match open parenthesis. - Fixed GUC FW version check to use XE_UC_FW_VER_RELEASE which points to current GUC FW version instead of XE_UC_FW_VER_COMPATIBILITY which holds GUC FW I/F version (Badal). v3: - Removed extra character in debug print. Signed-off-by:Karthik Poosa <karthik.poosa@intel.com> Reviewed-by:
-
Thomas Hellström authored
The last argument of xe_pcode_read() is a pointer. Use NULL instead of 0. Fixes: 92d44a42 ("drm/xe/hwmon: Expose card reactive critical power") Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Francois Dugast <francois.dugast@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240117134048.165425-6-thomas.hellstrom@linux.intel.com
-
Thomas Hellström authored
It is not referenced outside of the xe_dma_buf.c source file. Fixes: dd08ebf6 ("drm/xe: Introduce a new DRM driver for Intel GPUs") Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Signed-off-by:
-
- 16 Jan, 2024 2 commits
-
-
Lucas De Marchi authored
Creating one module for each compilation unit to be tested seems excessive as the number of tests increase. Group them all in a single kunit test module called xe_test.ko. The tests requiring the physical device, aka "live" tests, are still kept in separate modules since they are normally triggered via igt, and not via kunit.py. After igt is converted, those can be merged in a single module as well. Signed-off-by:
-
Michal Wajdeczko authored
There is no need to copy string step by step, use existing helper. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
-
- 12 Jan, 2024 6 commits
-
-
Jani Nikula authored
Remove the DRM_XE_DISPLAY config dependency on EXPERT. I can only presume the idea was only experts should be able to disable it, but the effect is the opposite. Reported-by:
Eero Tamminen <eero.t.tamminen@intel.com> Reviewed-by:
-
Brian Welty authored
Requesting all memory regions on PVC will fill bo->placements up to XE_BO_MAX_PLACEMENTS. The subsequent call to try_add_stolen() will trip over the bounds checking even though XE_PL_STOLEN is not expected to be used in this case. This is hit with igt@xe_exec_fault_mode@once-basic-prefetch: xe 0000:8c:00.0: [drm] Assertion `*c < (sizeof(bo->placements) / sizeof((bo->placements)[0]) + ((int)(sizeof(struct { int:(-!!(__builtin_types_compatible_p(typeof((bo->placements)), typeof(&(bo->placements)[0])))); }))))` failed! WARNING: CPU: 30 PID: 6161 at drivers/gpu/drm/xe/xe_bo.c:203 __xe_bo_placement_for_flags+0x218/0x240 [xe] Is fixed here by moving the bounds checks closer to where we actually write into the bo->placement array. Fixes: 8c54ee8a ("drm/xe: Ensure that we don't access the placements array out-of-bounds") Link: https://patchwork.freedesktop.org/patch/msgid/20240111002111.10190-1-brian.welty@intel.comSigned-off-by:Brian Welty <brian.welty@intel.com> Reviewed-by:
-
Matt Roper authored
Although MI_STORE_DATA_IMM's "length" field is 10-bits, 0x3FE is considered the largest legal value accepted. Since that instruction field is always encoded in (val-2) format, this translates to 0x400 dwords for the true maximum length of the instruction. Subtracting the instruction header (1 dword) and address (2 dwords), that leaves 0x3FD dwords (i.e., 0x1FE qwords) for PTE values. Bspec: 60246, 45753 Reviewed-by:
-
Michal Wajdeczko authored
If Doorbell Manager is in unclean state during fini phase, for debug purposes we try to print it's state, but we missed the fact that we are already holding a lock so the xe_guc_db_mgr_print() will deadlock since it also attempts to grab the same lock. Fixes: 587c7334 ("drm/xe: Introduce GuC Doorbells Manager") Cc: Piotr Piórkowski <piotr.piorkowski@intel.com> Reviewed-by:
Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://lore.kernel.org/r/20240111185603.673-1-michal.wajdeczko@intel.comSigned-off-by:
-
Michal Wajdeczko authored
Soon we will be required to exclude some of the GGTT addresses from the allocations, since on some platforms running the SR-IOV VF mode, we will be able to use only selected range of the GGTT space. Add helper functions to manage such GGTT range exclusions, and follow the naming from the similar concept used by GVT-g. Reviewed-by:
-
Michal Wajdeczko authored
While parsing and processing CTB G2H messages we should extract underlying HXG message and use HXG definitions on such message. Using outer CTB layer message in HXG definitions require use of shifted dword index, which might be confusing: FIELD_GET(GUC_HXG_MSG_0_xxx, msg[1]) instead of: FIELD_GET(GUC_HXG_MSG_0_xxx, hxg[0]) Cc: Matthew Brost <matthew.brost@intel.com> Reviewed-by:
-
- 11 Jan, 2024 7 commits
-
-
Michal Wajdeczko authored
Not all CTB responses from the GuC are fixed size and we need to pass response length to the caller, if there was a response_buffer. Easiest solution is to return it as positive value from all xe_guc_ct_send_recv() functions. The CTB response length is always between 1 and 254 (ie. GUC_HXG_MSG_MIN_LEN and GUC_CTB_MAX_DWORDS - GUC_HXG_MSG_MIN_LEN). Cc: Matthew Brost <matthew.brost@intel.com> Reviewed-by:
-
Michal Wajdeczko authored
Once GuC replied with GUC_HXG_TYPE_NO_RESPONSE_BUSY message then we may expect that only RESPONSE_SUCCESS or FAILURE message will be sent, anything else is a violation of the HXG protocol. Cc: Matthew Brost <matthew.brost@intel.com> Reviewed-by:
-
Michal Wajdeczko authored
Soon we will be trying to communicate with the GuC firmware very early during VF driver probe, before we finish normal init steps. Split GuC communication initialization code so the GuC MMIO based communication xe_guc_mmio_send() functions will work where needed. Cc: Matthew Brost <matthew.brost@intel.com> Reviewed-by:
-
Thomas Hellström authored
Since the migrate code is using the identity map for addressing VRAM, copy chunks may become as small as 64K if the VRAM resource is fragmented. However, a chunk size smaller that 1MiB may lead to the *next* chunk's offset into the CCS metadata backup memory may not be page-aligned, and the XY_CTRL_SURF_COPY_BLT command can't handle that, and even if it could, the current code doesn't handle the offset calculaton correctly. To fix this, make sure we align the size of VRAM copy chunks to 1MiB. If the remaining data to copy is smaller than that, that's not a problem, so use the remaining size. If the VRAM copy cunk becomes fragmented due to the size alignment restriction, don't use the identity map, but instead emit PTEs into the page-table like we do for system memory. v2: - Rebase v3: - Future proof somewhat by taking into account the real data size to flat CCS metadata size ratio. (Matt Roper) - Invert a couple of if-statements for better readability. - Fix support for 4K-granularity VRAM sizes. (Tested on DG1). v4: - Fix up code comments - Fix debug printout format typo. v5: - Add a Fixes: tag. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> Cc: Matthew Brost <matthew.brost@intel.com> Fixes: e89b384c ("drm/xe/migrate: Update emit_pte to cope with a size level than 4k") Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240110163415.524165-1-thomas.hellstrom@linux.intel.com
-
Dan Carpenter authored
Drop the "&vm->lock" before returning. Fixes: 24f947d5 ("drm/xe: Use DRM GPUVM helpers for external- and evicted objects") Signed-off-by:
Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by:
-
Dan Carpenter authored
Check if "bo" is an error pointer before calling xe_bo_lock() on it. Fixes: d6abc18d ("drm/xe/xe2: Modify xe_bo_test for system memory") Signed-off-by:
-
Dan Carpenter authored
This error path should clean up before returning. Smatch detected this bug: drivers/gpu/drm/xe/xe_device.c:487 xe_device_probe() warn: missing unwind goto? Fixes: 4cb12b71 ("drm/xe/xe2: Determine bios enablement for flat ccs on igfx") Signed-off-by:
-
- 10 Jan, 2024 7 commits
-
-
Matthew Brost authored
Convention for queues in Linux is the producer moves the head and consumer moves the tail. Fix the access counter queue to conform to this convention. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
-
Matthew Brost authored
If ACC_QUEUE_NUM_DW % ACC_MSG_LEN_DW != 0 then the access counter queue logic does not work when wrapping occurs. Add a build bug on to assert ACC_QUEUE_NUM_DW % ACC_MSG_LEN_DW == 0 to enforce this restriction and document the code. v2: - s/NUM_ACC_QUEUE/ACC_QUEUE_NUM_DW (Brian) Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
-
Matthew Brost authored
Convention for queues in Linux is the producer moves the head and consumer moves the tail. Fix the page fault queue to conform to this convention. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
-
Matthew Brost authored
If PF_QUEUE_NUM_DW % PF_MSG_LEN_DW != 0 then the page fault queue logic does not work when wrapping occurs. Add a build bug on to assert PF_QUEUE_NUM_DW % PF_MSG_LEN_DW == 0 to enforce this restriction and document the code. v2: - s/NUM_PF_QUEUE/PF_QUEUE_NUM_DW (Brian) Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
-
Brian Welty authored
This function is no longer used as the job_timeout is now updated prior to calling queue_ops.init(). Signed-off-by:
-
Brian Welty authored
Setting of exec_queue user extensions is moved from the end of the ioctl function earlier, into __xe_exec_queue_alloc(). This fixes bug in that the USM attributes for access counters were being applied too late, and effectively were ignored. However, in order to apply user extensions this early, we can no longer call q->ops functions. Instead, make it more efficient. The user extension functions can simply update the q->sched_props values and they will be applied by the backend during q->ops->init(). v2: minor changes for readability (Matt) Signed-off-by:
-
Brian Welty authored
The purpose here is to allow to optimize exec_queue_set_job_timeout() in follow-on patch. Currently it does q->ops->set_job_timeout(...). But we'd like to apply exec_queue_user_extensions much earlier and q->ops cannot be called before __xe_exec_queue_init(). It will be much more efficient to instead only have to set q->sched_props.job_timeout_ms when applying user extensions. That value will then be used during q->ops->init(). Signed-off-by:
-
