- 18 Mar, 2012 4 commits
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Carsten Emde authored
Following the documentation of the Legacy Backlight Brightness (LBB) Register in the configuration space of some Intel PCI graphics adapters, setting the LBB register with the value 0x0 causes the backlight to be turned off, and 0xFF causes the backlight to be set to 100% intensity (http://download.intel.com/embedded/processors/Whitepaper/324567.pdf). The Acer Aspire 5734Z, however, turns the backlight off at 0xFF and sets it to maximum intensity at 0. In consequence, the screen of this systems becomes dark at an early boot stage which makes it unusable. The same inversion applies to the BLC_PWM_CTL I915 register. This problem was introduced in kernel version 2.6.38 when the PCI device of this system was first supported by the i915 KMS module. This patch adds a parameter to the i915 module to enable inversion of the brightness variable (i915.invert_brightness). Signed-off-by:
Carsten Emde <C.Emde@osadl.org> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Sean Paul authored
I have seen a number of "blt ring initialization failed" messages where the ctl or start registers are not the correct value. Upon further inspection, if the code just waited a little bit, it would read the correct value. Adding the wait_for to these reads should eliminate the issue. Signed-off-by:
Sean Paul <seanpaul@chromium.org> Reviewed-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
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Adam Jackson authored
Some newer BIOSes are shipping with all MTRRs already populated. These BIOSes are all on machines with sufficiently new CPUs that the referenced errata doesn't apply anyway, so just don't try to claim the MTRR. Signed-off-by:
Adam Jackson <ajax@redhat.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41648Signed-off-by:
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Adam Jackson authored
No functional change here, just clarifying code flow. Signed-off-by:
Kenneth Graunke <kenneth@whitecape.org> Signed-off-by:
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- 02 Mar, 2012 2 commits
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Sean Paul authored
According to the PRM (Vol3P2), the PCH FDI receiver ISR read for bit lock should be retried at least once. This patch retries the read 5 times with a small delay in between reads. I've had reports of display corruption on resume with "FDI train 1 fail!", so I'm hoping that adding this retry will mitigate the issue. Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Jesse Barnes authored
They're not really errors (well actually I don't know; I don't understand _DSM and _MUX well enough to say, but I do know they spam people's logs and seem to be harmless). Signed-off-by:
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- 01 Mar, 2012 2 commits
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Mathias Fröhlich authored
This change enables the use of displays where the vbt table just contains inappropriate values, but either the vesa defaults or the video=... modes do something sensible with the attached display. The problem happens with an embedded board that contains vbt bios tables that do not match the attached display. Using this change and the appropriate kernel boot command line they are able to use an otherwise completely unusable secondary display on that embedded board. Reviewed-by:
Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by:
Mathias Froehlich <Mathias.Froehlich@web.de> Signed-off-by:
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Chris Wilson authored
By clearing the GPU read domains before waiting upon the buffer, we run the risk of the wait being interrupted and the domains prematurely cleared. The next time we attempt to wait upon the buffer (after userspace handles the signal), we believe that the buffer is idle and so skip the wait. There are a number of bugs across all generations which show signs of an overly haste reuse of active buffers. Such as: https://bugs.freedesktop.org/show_bug.cgi?id=29046 https://bugs.freedesktop.org/show_bug.cgi?id=35863 https://bugs.freedesktop.org/show_bug.cgi?id=38952 https://bugs.freedesktop.org/show_bug.cgi?id=40282 https://bugs.freedesktop.org/show_bug.cgi?id=41098 https://bugs.freedesktop.org/show_bug.cgi?id=41102 https://bugs.freedesktop.org/show_bug.cgi?id=41284 https://bugs.freedesktop.org/show_bug.cgi?id=42141 A couple of those pre-date i915_gem_object_finish_gpu(), so may be unrelated (such as a wild write from a userspace command buffer), but this does look like a convincing cause for most of those bugs. Signed-off-by:
Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by:
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- 29 Feb, 2012 8 commits
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Daniel Vetter authored
With the rework to merge the bit-banging fallback into the gmbus i2c adapter we've gotten rid of the deadlock possibility that originally lead to the disabling of this code. This reverts the revert commit 826c7e41 Author: Jean Delvare <khali@linux-fr.org> Date: Sat Jun 4 19:34:56 2011 +0000 Revert "drm/i915: Enable GMBUS for post-gen2 chipsets" Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=35572Reviewed-by:
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Daniel Vetter authored
This way we can simplify the setup and teardown a bit. Because we don't actually allocate anything anymore for the force_bit case, we can now convert that into a boolean. Also and the functionality supported by the bit-banging together with what gmbus can do, so that this doesn't randomly change any more. v2: Chris Wilson noticed that I've mixed up && and & ... v3: Clarify an if block as suggested by Eugeni Dodonov. Reviewed-by:
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Daniel Vetter authored
... and directly call the newly exported i2c bit-banging functions. The code is still pretty convoluted because we only set up the gpio i2c stuff when actually falling back, resulting in more complexity than necessary. This will be fixed up in the next patch. v2: Use exported i2c_bit_algo vtable instead of exported functions. Reviewed-by:
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Daniel Vetter authored
When we set up the gpio fallback, we always have a 1:1 relationship with an intel_gmbus. Exploit that to store all gpio related data in there, too. This is a preparation step to merge the tw i2c adapters controlling the same bus into one. Just mundane code-munging in this patch. Reviewed-by:
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Daniel Vetter authored
i915 has a hw i2c controller (gmbus) but for a bunch of stupid reasons we need to be able to fall back to the bit-banging algo on gpio pins. The current code sets up a 2nd i2c controller for the same i2c bus using the bit-banging algo. This has a bunch of issues, the major one being that userspace can directly access this fallback i2c adaptor behind the drivers back. But we need to frob a few registers before and after using fallback gpio bit-banging, so this horribly fails. The new plan is to only set up one i2c adaptor and transparently fall back to bit-banging by directly calling the xfer function of the bit- banging algo in the i2c core. To make that possible, export the 2 i2c algo functions. v2: As suggested by Jean Delvare, simply export the i2c_bit_algo vtable instead of the individual functions. Acked-by:
Jean Delvare <khali@linux-fr.org> Signed-off-by:
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Daniel Vetter authored
I'd like to export the corresponding functions from the i2c core so that I can use them in fallback bit-banging in i915.ko v2: Adapt to new i2c export patch. Cc: nouveau@lists.freedesktop.org Acked-by:
Dave Airlie <airlied@gmail.com> Signed-off-by:
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Daniel Vetter authored
This way we can free up the bus->adaptor.algo_data pointer and make it available for use with the bitbanging fallback algo. Reviewed-by:
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Benson Leung authored
gmbus_xfer with a single message (particularly a single message write) would set Bus Cycle Select to 100b, the Gen Stop cycle, instead of 101b, No Index, Stop cycle. This would not start single message i2c transactions. Also, gmbus_xfer done: will disable the interface without checking if it is idle. In the case of writes, there will be no wait on status or delay to ensure the write starts and completes before the interface is turned off. Fixed the former issue by using the same cycle selection as used in the I2C_M_RD for the write case. GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) Fixed the latter by waiting on GMBUS_ACTIVE to deassert before disable. Note from the grumpy d-i-n maintainer: The first hunk that changes the gmbus read path is just cosmetics to align the code with the write path. I.e. the commit message above is slightly lying because the first issue is _only_ with writes (and not simply "particularly"). Signed-off-by:
Benson Leung <bleung@chromium.org> Reviewed-by:
Daniel Kurtz <djkurtz@chromium.org> Signed-off-by:
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- 27 Feb, 2012 8 commits
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Daniel Vetter authored
gcc seems to get uber-anal recently about these things. Clarification from Dan Carpenter: "Sorry, I should have said that it's not a gcc warning, it's a smatch thing. But also it's not uber-anal. It's the exact level of anality which is required to make the == -1 test work. You can compare unsigned int and longs to -1 and it works but for smaller types it doesn't." Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Chris Wilson authored
This error message has since been superseded by the hangcheck, and does not add any salient information beyond that already printed by hangcheck discovering the GPU hang that lead to i915_wait_request() bombing out in the first place. Signed-off-by:
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Daniel Vetter authored
While fixing up a merge conflict with drm-next I've noticed that we use the same audio drm connector property also for dp and sdvo outputs. So put the new enum to some good use and convert these paths, too. The HDMI_AUDIO_ prefix is a bit a misnomer. But at least for sdvo it makes sense (and you can also connect a hdmi monitor with a dp->hdmi cable), so I've decided to stick with it. Reviewed-by:
Wu Fengguang <fengguang.wu@intel.com> Signed-Off-by:
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Chris Wilson authored
Retiring requests does not typically free up space in the aperture, so the additional search is pointless. Signed-off-by:
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Chris Wilson authored
Incrementing the reference count on all objects walked when searching for space in the aperture is a non-neglible amount of overhead. In fact, we only need to hold on to a reference for objects that we will evict, so we can therefore delay the referencing until we find a suitable hole and only add those objects that fall inside. Signed-off-by:
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Chris Wilson authored
As we warn the user later that we cannot find or load the VBIOS, explaining why is an exercise in debugging. Shouting *ERROR* upsets people and produces bug reports. Reported-by:
Michael Rieder <mr@student.ethz.ch> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43751Signed-off-by:
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Marc Gariepy authored
Add a no_lvds quirk for the HP t5745 and HP st5747 thin clients dmidecode for those thin clients are attached in thoses bugs: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/911916 https://bugs.launchpad.net/ubuntu/+source/linux/+bug/911920Signed-off-by:
Marc Gariepy <mgariepy@ubuntu.com> Acked-by:
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Philipp Grete authored
Fixes LP: #796030 by removing forced pipe A on HP 2730p. Quirk has previously been introduced to fix a sleep mode problem that does not exist any more. v2: Added Tested-by and Bugzilla Link Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/796030Tested-by:
Ronny Standtke <ronny.standtke@gmx.net> Signed-off-by:
Philipp Grete <mail@pgrete.de> Signed-off-by:
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- 23 Feb, 2012 1 commit
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Daniel Vetter authored
Manually resolve the conflict between the new enum drm property helpers in drm-next and the new "force-dvi" option that the "audio" output property gained in drm-intel-next. While resolving this conflict, switch the new drm_prop_enum_list to use the newly introduced enum defines instead of magic values. Conflicts: drivers/gpu/drm/i915/intel_modes.c Signed-Off-by:
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- 16 Feb, 2012 4 commits
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Dave Airlie authored
For the simple KMS driver case we need some more info about what the preferred depth and if a shadow framebuffer is preferred. I've only added this for intel/radeon which support the dumb ioctls so far. If you need something really fancy you should be writing a real X.org driver. v2: drop cursor information, just return an error from the cursor ioctls and we can make userspace fallback to sw cursor in that case, cursor info was getting too messy, best to start smaller. Signed-off-by:Dave Airlie <airlied@redhat.com>
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Dave Airlie authored
The current enabling of bus mastering in the drm midlayer allows a large race condition under kexec. When a kexec'ed kernel re-enables bus mastering for the GPU, previously setup dma blocks may cause writes to random pieces of memory. On radeon the writeback mechanism can cause these sorts of issues. This patch doesn't fix the problem, but it moves the bus master enable under the individual drivers control so they can move enabling it until later in their load cycle and close the race. Fix for radeon kms driver will be in a follow-up patch. Signed-off-by: -
Danny Kukawka authored
This reverts commit e167976e, Since this was already fixed in commit 3bd3c932 some days before this commit cause seq_file.h to be included twice. Signed-off-by:
Danny Kukawka <danny.kukawka@bisect.de> Signed-off-by:
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Dan Carpenter authored
We store stuff in texdw[7] so this array needs to have 8 elements. Signed-off-by:
Jerome Glisse <jglisse@redhat.com> Signed-off-by:
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- 15 Feb, 2012 4 commits
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Chris Wilson authored
With the introduction of the PCH, we gained an LVDS presence pin but we continued to use the existing logic that asserted that LVDS was only supported on certain mobile chipsets. However, there are desktop IronLake systems with LVDS attached which we fail to detect. So for PCH, trust the LVDS presence pin and quirk all the lying manufacturers. Tested-by:
Daniel Woff <wolff.daniel@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43171Signed-off-by:
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Chris Wilson authored
So that we can tally the request against the command sequence in the ringbuffer, or merely jump to the interesting locations. Signed-off-by:
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Chris Wilson authored
Being able to tally the list of outstanding requests with the sequence of commands in the ringbuffer is often useful evidence with respect to driver corruption. Note that since this is the umpteenth per-ring data structure to be added to the error state, I've coallesced the nearby loops (the ringbuffer and batchbuffer) into a single structure along with the list of requests. A later task would be to refactor the ring register state into the same structure. v2: Fix pretty printing of requests so that they are parsed correctly by intel_error_decode and use the 0x%08x format for seqno for consistency Signed-off-by:
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Chris Wilson authored
By recording the location of every request in the ringbuffer, we know that in order to retire the request the GPU must have finished reading it and so the GPU head is now beyond the tail of the request. We can therefore provide a conservative estimate of where the GPU is reading from in order to avoid having to read back the ring buffer registers when polling for space upon starting a new write into the ringbuffer. A secondary effect is that this allows us to convert intel_ring_buffer_wait() to use i915_wait_request() and so consolidate upon the single function to handle the complicated task of waiting upon the GPU. A necessary precaution is that we need to make that wait uninterruptible to match the existing conditions as all the callers of intel_ring_begin() have not been audited to handle ERESTARTSYS correctly. By using a conservative estimate for the head, and always processing all outstanding requests first, we prevent a race condition between using the estimate and direct reads of I915_RING_HEAD which could result in the value of the head going backwards, and the tail overflowing once again. We are also careful to mark any request that we skip over in order to free space in ring as consumed which provides a self-consistency check. Given sufficient abuse, such as a set of unthrottled GPU bound cairo-traces, avoiding the use of I915_RING_HEAD gives a 10-20% boost on Sandy Bridge (i5-2520m): firefox-paintball 18927ms -> 15646ms: 1.21x speedup firefox-fishtank 12563ms -> 11278ms: 1.11x speedup which is a mild consolation for the performance those traces achieved from exploiting the buggy autoreported head. v2: Add a few more comments and make request->tail a conservative estimate as suggested by Daniel Vetter. Signed-off-by:
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- 14 Feb, 2012 4 commits
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Paulo Zanoni authored
This was pointed by Jesse Barnes. The code now seems to follow the specification but I don't have an SDVO device to really test this. Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
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Dave Airlie authored
Merge tag 'drm-intel-next-2012-02-07' of git://people.freedesktop.org/~danvet/drm-intel into drm-core-next * tag 'drm-intel-next-2012-02-07' of git://people.freedesktop.org/~danvet/drm-intel: (29 commits) drm/i915: Handle unmappable buffers during error state capture drm/i915: rewrite shmem_pread_slow to use copy_to_user drm/i915: rewrite shmem_pwrite_slow to use copy_from_user drm/i915: fall through pwrite_gtt_slow to the shmem slow path drm/i915: add debugfs file for swizzling information drm/i915: fix swizzle detection for gen3 drm/i915: Remove the upper limit on the bo size for mapping into the CPU domain drm/i915: add per-ring fault reg to error_state drm/i915: reject GTT domain in relocations drm/i915: remove the i915_batchbuffer_info debugfs file drm/i915: capture error_state also for stuck rings drm/i915: refactor debugfs create functions drm/i915: refactor debugfs open function drm/i915: don't trash the gtt when running out of fences drm/i915: Separate fence pin counting from normal bind pin counting drm/i915/ringbuffer: kill snb blt workaround drm/i915: collect more per ring error state drm/i915: refactor ring error state capture to use arrays drm/i915: switch ring->id to be a real id drm/i915: set AUD_CONFIG N_value_index for DisplayPort ...
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Yufeng Shen authored
GMBUS has several ports and each has it's own corresponding I2C adpater. When multiple I2C adapters call gmbus_xfer() at the same time there is a race condition in using the underlying GMBUS controller. Fixing this by adding a mutex lock when calling gmbus_xfer(). v2: Moved gmbus_mutex below intel_gmbus and added comments. Rebased to drm-intel-next-queued. Signed-off-by:
Yufeng Shen <miletus@chromium.org> [danvet: Shortened the gmbus_mutex comment a bit and add the patch revision comment to the commit message.] Signed-off-by:
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Wu Fengguang authored
When HDMI-DVI converter is used, it's not only necessary to turn off audio, but also to disable HDMI_MODE_SELECT and video infoframe. Since the DVI mode is mainly tied to audio functionality from end user POV, add a new "force-dvi" audio mode: xrandr --output HDMI1 --set audio force-dvi Note that most users won't need to set this and happily rely on the EDID based DVI auto detection. Reported-by:
Andrea Arcangeli <aarcange@redhat.com> Signed-off-by:
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- 13 Feb, 2012 3 commits
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Sean Paul authored
This patch replaces the locking from the downclock routines with an assert to ensure the registers are indeed unlocked. Without this patch, pre-SNB devices would lock the registers when downclocking which would cause a WARNING on suspend/resume with downclocking enabled. Note: To hit this bug, you need to have lvds downclocking enabled. Signed-off-by:
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Jerome Glisse authored
evergreen and northern island gpu needs more informations for 2D tiling than previous r6xx/r7xx. Add field to tiling ioctl to allow userspace to provide those. The v8 cs checking change to track color view on r6xx/r7xx doesn't affect old userspace as old userspace always emited 0 for this register. v2 fix r6xx/r7xx 2D tiling computation v3 fix r6xx/r7xx height align for untiled surface & add support for tile split on evergreen and newer v4 improve tiling debugging output v5 fix tile split code for evergreen and newer v6 set proper tile split for crtc register v7 fix tile split limit value v8 add COLOR_VIEW checking to r6xx/r7xx checker, add evergreen cs checking, update safe reg for r600, evergreen and cayman. Evergreen checking need some work around for stencil alignment issues v9 fix tile split value range, fix compressed texture handling and mipmap calculation, allow evergreen check to be silencious in front of current broken userspace (depth/stencil alignment issue) v10 fix eg 3d texture and compressed texture, fix r600 depth array, fix r600 color view computation, add support for evergreen stencil split v11 more verbose debugging in some case Signed-off-by: -
Marek Olšák authored
v2: agd5f: add strmout CS checking, copy_dw register checking v3: agd5f: don't use cs_check_reg() for copy_dw checking as it will incorrectly patch the command stream for certain regs. v4: agd5f: add warning if safe reg check fails for copy_dw v5: agd5f: add stricter checking for 6xx/7xx v6: agd5f: add range checking for copy_dw on eg+, add sx_surface_sync to safe reg list for 7xx. v7: agd5f: add stricter checking for eg+ Signed-off-by:
Marek Olšák <maraeo@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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