- 10 Dec, 2020 14 commits
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Alex Deucher authored
It's only used when CONFIG_DRM_AMD_DC_DCN is set. Fixes and set but not used warning. Acked-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
The "COMPUTE" was wrongly spelled as "CUSTOM". Signed-off-by:
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Evan Quan authored
Fulfill the 2nd usb2.0 port workaround for sienna cichlid. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Evan Quan authored
The workaround is needed by sienna cichlid. Signed-off-by:
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Evan Quan authored
Used for determining 2ND_USB20PORT support from firmware_capability. Signed-off-by:
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Evan Quan authored
That will help to determine whether 2ND_USB20_PORT workaround is needed for Sienna Cichlid. Signed-off-by:
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Evan Quan authored
New SMC message was introduced for gpo control on sienna cichlid. Signed-off-by:
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Evan Quan authored
Correct the power limit setting for SMU V11 asics. Signed-off-by:
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Evan Quan authored
Enable power source switch on Sienna Cichlid. Signed-off-by:
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Jiansong Chen authored
Correct pipe offset calculation in is_pipe_enabled function, it should be done in queues. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
After refactor our amdgpu_dm_atomic_commit, this function only invoke drm_atomic_helper_commit. For this reason, this commit drops amdgpu_dm_atomic_commit and add drm_atomic_helper_commit directly in the atomic_commit hook. v2: squash in warning fix (Alex) Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Christian König authored
The text output should not be more than a page, so only print the first 32 page table entries. If we need all of them we can still look into the binary trace. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
amd-drm-next-5.11-2020-12-09: amdgpu: - SR-IOV fixes - Navy Flounder updates - Sienna Cichlid updates - Dimgrey Cavefish updates - Vangogh updates - Misc SMU fixes - Misc display fixes - Last big hunk of W=1 warning fixes - Cursor validation fixes - CI BACO updates From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201210045344.21566-1-alexander.deucher@amd.comSigned-off-by:
Dave Airlie <airlied@redhat.com>
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Andrey Grodzovsky authored
For BOs imported from outside of amdgpu, setting of amdgpu_gem_object_funcs was missing in amdgpu_dma_buf_create_obj. Fix by refactoring BO creation and amdgpu_gem_object_funcs setting into single function called from both code paths. Fixes: d693def4 ("drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver") v2: Use use amdgpu_gem_object_create() directly v3: fix warning Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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- 09 Dec, 2020 26 commits
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https://gitlab.freedesktop.org/drm/msmDave Airlie authored
* Shutdown hook for GPU (to ensure GPU is idle before iommu goes away) * GPU cooling device support * DSI 7nm and 10nm phy/pll updates * Additional sm8150/sm8250 DPU support (merge_3d and DSPP color processing) * Various DP fixes * A whole bunch of W=1 fixes from Lee Jones * GEM locking re-work (no more trylock_recursive in shrinker!) * LLCC (system cache) support * Various other fixes/cleanups Signed-off-by:
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Alex Deucher authored
If we need to keep the stolen vga memory, make sure it is at least as big as the legacy vga size. Acked-by:
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Alex Deucher authored
No longer used. Reviewed-by:
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Alex Deucher authored
Rather than in late_init to avoid race conditions between freeing the buffers and the initial modeset. Reviewed-by:
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Alex Deucher authored
Works using BACO. Reviewed-by:
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Alex Deucher authored
Works now that the BACO sequence is fixed. Reviewed-by:
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Changfeng authored
When using old WORKLOAD_PPLIB setting in smu10.h, there is problem that it can't be able to switch to mak gpu clk during compute workload. It needs to update WORKLOAD_PPLIB setting to fix this issue. Signed-off-by:
Changfeng <Changfeng.Zhu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Acked-by:
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Xiaojian Du authored
This patch is to remove one unsupported smu function, this function will set the smu feature mask to disable all smu features in exception. Because vangogh doesn't support to set the smu feature mask by driver software, so this function is invalid for vangogh. Signed-off-by:
Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by:
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Roman Li authored
[Why] Scatter/gather is APU feature. But in dm it is limited only to Renoir. Now we need it for Vangogh. [How] Apply system context setup in dm_init to all APUs. Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Roman Li authored
[Why] Scatter/gather feature is supported on Vangogh. [How] Add GTT domain support for Vangogh to enable display buffers in system memory. Signed-off-by:
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Felix Kuehling authored
Release dmabuf reference before returning from kfd_ioctl_import_dmabuf. amdgpu_amdkfd_gpuvm_import_dmabuf takes a reference to the underlying GEM BO and doesn't keep the reference to the dmabuf wrapper. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
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Nirmoy Das authored
Replace hardcoded vmid number with AMDGPU_NUM_VMID macro. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Acked-by:
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Stanley.Yang authored
each sdma instance fw_version and feature_version should be set right value when asic type isn't between SIENNA_CICHILD and CHIP_DIMGREY_CAVEFISH Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Tao Zhou authored
Per PMFW 59.16.0. Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Eryk Brol <eryk.brol@amd.com> Signed-off-by:
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Anthony Koo authored
- Add define for __forceinline Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
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Michael Strauss authored
[Why] New value breaks VSR on high refresh panels, reverting until a fix is developed Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Charlene Liu authored
[Why] dcn3_01 supports gpu_vm, but this is not enabled in amdgpu_dm Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
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Roy Chan authored
[Why] When HDCP is on, some display would introduce audio noise during HDCP handling. [How] Mute before HDCP handling when disabling core link. Unmute after HDCP when enabling core link. Signed-off-by:
Roy Chan <roy.chan@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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Sung Lee authored
[Why] Without additional HostVM Latency, Renoir takes 2us longer to exit self-refresh. This causes underflow in certain cases. [How] Add table for Renoir with updated sr exit latencies for WM set A. Signed-off-by:
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Chris Park authored
[Why] At very high pixel clock, bandwidth calculation exceeds 32 bit size and overflow value. This causes the resulting selection of link rate to be inaccurate. [How] Change order of operation and use fixed point to deal with integer accuracy. Also address bug found when forcing link rate. Signed-off-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Qingqing Zhuo authored
[Why] With the addition of dc_lock acquire before dc_link_handle_hpd_rx_irq, there will be a deadlock situation where commit state sends a request for payload allocation on MST and wait for HPD to process DOWN_REP. [How] Move forward the MST message handling in handle_hpd_rx_irq so that it will not rely on call to dc_link_handle_hpd_rx_irq. Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Wesley Chalmers authored
[Why] Currently, the offset provided to dcn30_set_disp_pattern_generator is not forwarded to OPP for display pattern generation, resulting in misaligned patterns and test failures. [How] Use the provided offset. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Acked-by:
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Judy Cai authored
[Why] Change in DCN10 to use IMMEDIATE_UPDATE mode for AFMT is not reflected in DCN30 as it uses VPG. [How] Use IMMEDIATE_UPDATE mode for DCN30 in VPG. Signed-off-by:
Judy Cai <HuiYi.Cai@amd.com> Reviewed-by:
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John Wu authored
[Why] power_down_on_boot is designed to power down HW when set mode is not called before timeout. It can happen in headless system or booting with the display is output by non-AMD GPU only. The function will be executed only if it's not seamless boot. So in seamless boot, the HW is still on. It's not necessary to check this since there's no display data in both cases. [How] Remove seamless boot checking in power_down_on_boot. Signed-off-by:
John Wu <john.wu@amd.com> Reviewed-by:
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Jing Zhou authored
[Why] Bump into calcReducedBlankingTiming because of mode query failed. In this function, timing.displayColorDepth == DISPLAY_COLOR_DEPTH_UNDEFINED. Then req_bw == 0 because of bits_per_channel == 0. So decide edp link settings, use default RBRx1 for special timing. [How] Set default bits_per_channel is 8. Signed-off-by:
Jing Zhou <Jing.Zhou@amd.com> Reviewed-by:
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