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  1. 15 Nov, 2016 8 commits
    • Maxime Ripard's avatar
      pinctrl: sunxi: Add support for interrupt debouncing · 7c926492
      Maxime Ripard authored 
      The pin controller found in the Allwinner SoCs has support for interrupts
debouncing.

However, this is not done per-pin, preventing us from using the generic
pinconf binding for that, but per irq bank, which, depending on the SoC,
ranges from one to five.

Introduce a device-wide property to deal with this using a microsecond
resolution. We can re-use the per-pin input-debounce property for that, so
let's do it!
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      7c926492
    • Chen-Yu Tsai's avatar
      pinctrl: sunxi: Make sunxi_pconf_group_set use sunxi_pconf_reg helper · 51814827
      Chen-Yu Tsai authored 
      The sunxi_pconf_reg helper introduced in the last patch gives us the
chance to rework sunxi_pconf_group_set to have it match the structure
of sunxi_pconf_(group_)get and make it easier to understand.

For each config to set, it:

    1. checks if the parameter is supported.
    2. checks if the argument is within limits.
    3. converts argument to the register value.
    4. writes to the register with spinlock held.

As a result the function now blocks unsupported config parameters,
instead of silently ignoring them.
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      51814827
    • Chen-Yu Tsai's avatar
      pinctrl: sunxi: Add support for fetching pinconf settings from hardware · c5fda170
      Chen-Yu Tsai authored 
      The sunxi pinctrl driver only caches whatever pinconf setting was last
set on a given pingroup. This is not particularly helpful, nor is it
correct.

Fix this by actually reading the hardware registers and returning
the correct results or error codes. Also filter out unsupported
pinconf settings. Since this driver has a peculiar setup of 1 pin
per group, we can support both pin and pingroup pinconf setting
read back with the same code. The sunxi_pconf_reg helper and code
structure is inspired by pinctrl-msm.

With this done we can also claim to support generic pinconf, by
setting .is_generic = true in pinconf_ops.

Also remove the cached config value. The behavior of this was never
correct, as it only cached 1 setting instead of all of them. Since
we can now read back settings directly from the hardware, it is no
longer required.
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      c5fda170
    • Chen-Yu Tsai's avatar
      pinctrl: sunxi: Fix PIN_CONFIG_BIAS_PULL_{DOWN,UP} argument · 223dba00
      Chen-Yu Tsai authored 
      According to pinconf-generic.h, the argument for
PIN_CONFIG_BIAS_PULL_{DOWN,UP} is non-zero if the bias is enabled
with a pull up/down resistor, zero if it is directly connected
to VDD or ground.

Since Allwinner hardware uses a weak pull resistor internally,
the argument should be 1.
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      223dba00
    • Chen-Yu Tsai's avatar
      pinctrl: sunxi: Free configs in pinctrl_map only if it is a config map · 88f01a1b
      Chen-Yu Tsai authored 
      In the recently refactored sunxi pinctrl library, we are only allocating
one set of pin configs for each pinmux setting node. When the pinctrl_map
structure is freed, the pin configs should also be freed. However the
code assumed the first map would contain the configs, which actually
never happens, as the mux function map gets added first.

The proper way to do this is to look through all the maps and free the
first one whose type is actually PIN_MAP_TYPE_CONFIGS_GROUP.

Also slightly expand the comment explaining this.

Fixes: f233dbca ("pinctrl: sunxi: Rework the pin config building code")
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      88f01a1b
    • Paul Gortmaker's avatar
      pinctrl: vt8500: make bool drivers explicitly non-modular · 23d511f6
      Paul Gortmaker authored 
      None of the Kconfigs for any of these drivers are tristate, meaning
that they currently are not being built as a module by anyone.

Lets remove the modular code that is essentially orphaned, so that
when reading the drivers there is no doubt they are builtin-only.  All
drivers get the exact same change, so they are handled in batch.

Changes are (1) use builtin_platform_driver, (2) use init.h header
(3) delete module_exit related code, (4) delete MODULE_DEVICE_TABLE,
(5) delete MODULE_LICENCE/MODULE_AUTHOR and associated tags and (6)
drop ".remove" code and prevent sysfs unbind attempts to call ".remove".

Once this is done, the shared remove function in wmt.[ch] is no longer
used and hence it is removed as well.

Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.

Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.

We also delete the MODULE_LICENSE etc. tags since all that information
is already contained at the top of each file in the comments.

Cc: Tony Prisk <linux@prisktech.co.nz>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      23d511f6
    • Chanwoo Choi's avatar
      pinctrl: samsung: Add GPF support for Exynos5433 · ac8130e9
      Chanwoo Choi authored 
      This patch add the support of GPF[1-5] pin of Exynos5433 SoC. The GPFx need
to support the multiple memory map because the registers of GPFx are located
in the different domain.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: default avatarJoonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      ac8130e9
    • Chanwoo Choi's avatar
      pinctrl: samsung: Add the support the multiple IORESOURCE_MEM for one pin-bank · 8b1bd11c
      Chanwoo Choi authored 
      This patch supports the multiple IORESOURCE_MEM resources for one pin-bank.
In the pre-existing Exynos series, the registers of the gpio bank are included
in the one memory map. But, some gpio bank need to support the one more memory
map (IORESOURCE_MEM) because the registers of gpio bank are separated into
the different memory map.

For example,
The both ALIVE and IMEM domain have the different memory base address.
The GFP[1-5] of exynos5433 are composed as following:
- ALIVE domain : WEINT_* registers
- IMEM domain  : CON/DAT/PUD/DRV/CONPDN/PUDPDN register

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: linux-gpio@vger.kernel.org
Suggested-by: default avatarTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      8b1bd11c
  3. 14 Nov, 2016 2 commits
  5. 11 Nov, 2016 2 commits
  7. 08 Nov, 2016 19 commits
  9. 07 Nov, 2016 1 commit
  11. 04 Nov, 2016 8 commits
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