1. 10 Jun, 2016 2 commits
  2. 09 Jun, 2016 33 commits
  3. 08 Jun, 2016 1 commit
    • Stefan Agner's avatar
      drm/fsl-dcu: use flat regmap cache · ce492b3b
      Stefan Agner authored
      Using flat regmap cache instead of RB-tree to avoid the following
      lockdep warning on driver load:
      WARNING: CPU: 0 PID: 1 at kernel/locking/lockdep.c:2755 lockdep_trace_alloc+0x15c/0x160()
      DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags))
      
      The RB-tree regmap cache needs to allocate new space on first
      writes. However, allocations in an atomic context (e.g. when a
      spinlock is held) are not allowed. The function regmap_write
      calls map->lock, which acquires a spinlock in the fast_io case.
      Since the FSL DCU driver uses MMIO, the regmap bus of type
      regmap_mmio is being used which has fast_io set to true.
      
      Use flat regmap cache and specify max register to be large
      enouth to cover all registers available in LS1021a and Vybrids
      register space.
      Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
      Cc: Mark Brown <broonie@kernel.org>
      Cc: stable@vger.kernel.org
      ce492b3b
  4. 06 Jun, 2016 4 commits
    • Ben Skeggs's avatar
      drm/nouveau/disp/sor/gm107: training pattern registers are like gm200 · 4691409b
      Ben Skeggs authored
      Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
      Cc: stable@vger.kernel.org
      4691409b
    • Ben Skeggs's avatar
      drm/nouveau/disp/sor/gf119: both links use the same training register · a8953c52
      Ben Skeggs authored
      It appears that, for whatever reason, both link A and B use the same
      register to control the training pattern.  It's a little odd, as the
      GPUs before this (Tesla/Fermi1) have per-link registers, as do newer
      GPUs (Maxwell).
      
      Fixes the third DP output on NVS 510 (GK107).
      Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
      Cc: stable@vger.kernel.org
      a8953c52
    • Mario Kleiner's avatar
      drm/vc4: Make pageflip completion handling more robust. · 56d1fe09
      Mario Kleiner authored
      Protect both the setup of the pageflip event and the
      latching of the new requested displaylist head pointer
      by the event lock, so we can't get into a situation
      where vc4_atomic_flush latches the new display list via
      HVS_WRITE, then immediately gets preempted before queueing
      the pageflip event, then the page-flip completes in hw and
      the vc4_crtc_handle_page_flip() runs and no-ops due to
      lack of a pending pageflip event, then vc4_atomic_flush
      continues and only then queues the pageflip event - after
      the page flip handling already no-oped. This would cause
      flip completion handling only at the next vblank - one
      frame too late.
      
      In vc4_crtc_handle_page_flip() check the actual DL head
      pointer in SCALER_DISPLACTX against the requested pointer
      for page flip to make sure that the flip actually really
      completed in the current vblank and doesn't get deferred
      to the next one because the DL head pointer was written
      a bit too late into SCALER_DISPLISTX, after start of
      vblank, and missed the boat. This avoids handling a
      pageflip completion too early - one frame too early.
      
      According to Eric, DL head pointer updates which were
      written into the HVS DISPLISTX reg get committed to hardware
      at the last pixel of active scanout. Our vblank interrupt
      handler, as triggered by PV_INT_VFP_START irq, gets to run
      earliest at the first pixel of HBLANK at the end of the
      last scanline of active scanout, ie. vblank irq handling
      runs at least 1 pixel duration after a potential pageflip
      completion happened in hardware.
      
      This ordering of events in the hardware, together with the
      lock protection and SCALER_DISPLACTX sampling of this patch,
      guarantees that pageflip completion handling only runs at
      exactly the vblank irq of actual pageflip completion in all
      cases.
      
      Background info from Eric about the relative timing of
      HVS, PV's and trigger points for interrupts, DL updates:
      
      https://lists.freedesktop.org/archives/dri-devel/2016-May/107510.html
      
      Tested on RPi 2B with hardware timing measurement equipment
      and shown to no longer complete flips too early or too late.
      Signed-off-by: default avatarMario Kleiner <mario.kleiner.de@gmail.com>
      Reviewed-by: default avatarEric Anholt <eric@anholt.net>
      56d1fe09
    • Herve Jourdain's avatar
      drm/vc4: Fix ioctl permissions for render nodes. · b10c22e5
      Herve Jourdain authored
      Contrary to other flags to DRM_IOCTL_DEF_DRV(), which restrict usage,
      the flag for render node is an enabler (the IOCTL can't be used from
      render node if it's not present).  So DRM_RENDER_ALLOW needs to be
      added to all the flags that were previously 0.
      Signed-off-by: default avatarHerve Jourdain <herve.jourdain@neuf.fr>
      Reviewed-by: default avatarEric Anholt <eric@anholt.net>
      Fixes: 0cd3e274 ("drm/vc4: Add missing render node support")
      b10c22e5