- 09 Feb, 2022 8 commits
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Ville Syrjälä authored
Hoist the IPS related vblank waits one level up. Later on we'll want to consolidate all the potential pre-plane update vblank waits into one so we can't be hiding any in low level code. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220209113526.7595-1-ville.syrjala@linux.intel.comReviewed-by:
Jani Nikula <jani.nikula@intel.com>
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Jani Nikula authored
The struct is only needed in intel_pm.c, move it there. Signed-off-by:
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Jani Nikula authored
The struct is only needed in intel_dpll.c, move it there. Signed-off-by:
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Jani Nikula authored
Avoid referencing the function pointer directly to be able to abstract the call better. Signed-off-by:
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Jani Nikula authored
The struct is only needed in intel_fdi.c, move it there. Signed-off-by:
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Jani Nikula authored
With intel_hpd_irq_setup() in i915_irq.c, struct intel_hotplug_funcs is also only needed there. Signed-off-by:
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Jani Nikula authored
The struct is only needed in intel_color.c, move it there. Signed-off-by:
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Jani Nikula authored
Group the forward declarations in i915_drv.h together near the top, like in other header files, and sort. Signed-off-by:
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- 08 Feb, 2022 3 commits
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Ville Syrjälä authored
The bogus loop from compute_dbuf_slices() was copied into check_mbus_joined() as well. So this lookup is wrong as well. Fix it. Cc: stable@vger.kernel.org Fixes: f4dc0086 ("drm/i915/adl_p: MBUS programming") Signed-off-by:
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Ville Syrjälä authored
Apparently I totally fumbled the loop condition when I removed the ARRAY_SIZE() stuff from the dbuf slice config lookup. Comparing the loop index with the active_pipes bitmask is utter nonsense, what we want to do is check to see if the mask is zero or not. Note that the code actually ended up working correctly despite the fumble, up until commit eef17395 ("drm/i915: Allow !join_mbus cases for adlp+ dbuf configuration") when things broke for real. Cc: stable@vger.kernel.org Fixes: 05e8155a ("drm/i915: Use a sentinel to terminate the dbuf slice arrays") Signed-off-by:
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Lucas De Marchi authored
Rename struct dma_buf_map to struct iosys_map and corresponding APIs. Over time dma-buf-map grew up to more functionality than the one used by dma-buf: in fact it's just a shim layer to abstract system memory, that can be accessed via regular load and store, from IO memory that needs to be acessed via arch helpers. The idea is to extend this API so it can fulfill other needs, internal to a single driver. Example: in the i915 driver it's desired to share the implementation for integrated graphics, which uses mostly system memory, with discrete graphics, which may need to access IO memory. The conversion was mostly done with the following semantic patch: @r1@ @@ - struct dma_buf_map + struct iosys_map @r2@ @@ ( - DMA_BUF_MAP_INIT_VADDR + IOSYS_MAP_INIT_VADDR | - dma_buf_map_set_vaddr + iosys_map_set_vaddr | - dma_buf_map_set_vaddr_iomem + iosys_map_set_vaddr_iomem | - dma_buf_map_is_equal + iosys_map_is_equal | - dma_buf_map_is_null + iosys_map_is_null | - dma_buf_map_is_set + iosys_map_is_set | - dma_buf_map_clear + iosys_map_clear | - dma_buf_map_memcpy_to + iosys_map_memcpy_to | - dma_buf_map_incr + iosys_map_incr ) @@ @@ - #include <linux/dma-buf-map.h> + #include <linux/iosys-map.h> Then some files had their includes adjusted and some comments were update to remove mentions to dma-buf-map. Since this is not specific to dma-buf anymore, move the documentation to the "Bus-Independent Device Accesses" section. v2: - Squash patches v3: - Fix wrong removal of dma-buf.h from MAINTAINERS - Move documentation from dma-buf.rst to device-io.rst v4: - Change documentation title and level Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Acked-by:
Christian König <christian.koenig@amd.com> Acked-by:
Sumit Semwal <sumit.semwal@linaro.org> Acked-by:
Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20220204170541.829227-1-lucas.demarchi@intel.com
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- 07 Feb, 2022 4 commits
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Lucas De Marchi authored
Remove the trailing semicolon, as correctly warned by checkpatch: -:1189: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon #1189: FILE: drivers/gpu/drm/i915/intel_device_info.c:119: +#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name)); Signed-off-by:
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Ville Syrjälä authored
On TGL/RKL the BIOS likes to use some kind of bogus DBUF layout that doesn't match what the spec recommends. With a single active pipe that is not going to be a problem, but with multiple pipes active skl_commit_modeset_enables() goes into an infinite loop since it can't figure out any order in which it can commit the pipes without causing DBUF overlaps between the planes. We'd need some kind of extra DBUF defrag stage in between to make the transition possible. But that is clearly way too complex a solution, so in the name of simplicity let's just sanitize the DBUF state by simply turning off all planes when we detect a pipe encroaching on its neighbours' DBUF slices. We only have to disable the primary planes as all other planes should have already been disabled (if they somehow were enabled) by earlier sanitization steps. And for good measure let's also sanitize in case the DBUF allocations of the pipes already seem to overlap each other. Cc: <stable@vger.kernel.org> # v5.14+ Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4762Signed-off-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
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Ville Syrjälä authored
During readout we cannot assume the planes are actually using the slices they are supposed to use. The BIOS may have misprogrammed things and put the planes onto the wrong dbuf slices. So let's do the readout more carefully to make sure we really know which dbuf slices are actually in use by the pipe at the time. Cc: <stable@vger.kernel.org> # v5.14+ Signed-off-by:
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Ville Syrjälä authored
Reintroduce the !join_mbus single pipe cases for adlp+. Due to the mbus relative dbuf offsets in PLANE_BUF_CFG we need to know the actual slices used by the pipe when doing readout, even when mbus joining isn't enabled. Accurate readout will be needed to properly sanitize invalid BIOS dbuf configurations. This will also make it much easier to play around with the !join_mbus configs for testin/workaround purposes. Cc: <stable@vger.kernel.org> # v5.14+ Signed-off-by:
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- 03 Feb, 2022 3 commits
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Imre Deak authored
Make sure all unused power wells left enabled by BIOS get disabled during driver loading and system resume. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5028Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
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Lucas De Marchi authored
Architectures others than x86 have a stub implementation calling WARN_ON_ONCE(). The appropriate headers need to be included, otherwise the header-test target will fail with: HDRTEST drivers/gpu/drm/i915/i915_mm.h In file included from <command-line>: ./drivers/gpu/drm/i915/i915_mm.h: In function ‘remap_io_mapping’: ./drivers/gpu/drm/i915/i915_mm.h:26:2: error: implicit declaration of function ‘WARN_ON_ONCE’ [-Werror=implicit-function-declaration] 26 | WARN_ON_ONCE(1); | ^~~~~~~~~~~~ v2: Do not include <linux/printk.h> since call to pr_err() has been removed Fixes: 67c430bb ("drm/i915: Skip remap_io_mapping() for non-x86 platforms") Cc: Siva Mullati <siva.mullati@intel.com> Signed-off-by:Siva Mullati <siva.mullati@intel.com> Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220131165926.3230642-3-lucas.demarchi@intel.com
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Lucas De Marchi authored
Following what was done in drm_cache.c, when the stub for remap_io_mapping() was added in commit 67c430bb ("drm/i915: Skip remap_io_mapping() for non-x86 platforms"), it included a log message with pr_err(). However just the warning is already enough and switching to WARN_ONCE() allows us to keep the log message while avoiding log spam. Signed-off-by:
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- 02 Feb, 2022 9 commits
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Matt Roper authored
A couple hunks didn't get applied while resolving the conflicts on commit 0d6419e9 ("drm/i915: Move GT registers to their own header file"). Add the second half of the patch as a follow-up commit. Fixes: 0d6419e9 ("drm/i915: Move GT registers to their own header file") Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
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Matt Roper authored
Several of our i915 header files, have been including i915_reg.h. This means that any change to i915_reg.h will trigger a full rebuild of pretty much every file of the driver, even those that don't have any kind of register access. Let's delete the i915_reg.h include from all headers and add an explicit include from the .c files that truly need the register definitions; those that need a definition of i915_reg_t for a function definition can get it from i915_reg_defs.h instead. We also remove two non-register #define's (VLV_DISPLAY_BASE and GEN12_SFC_DONE_MAX) into i915_reg_defs.h to allow us to drop the i915_reg.h include from a couple of headers. There's probably a lot more header dependency optimization possible, but the changes here roughly cut the number of files compiled after 'touch i915_reg.h' in half --- a good first step. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Matt Roper authored
This is a huge, chaotic mass of registers copied over as-is without any real cleanup. We'll come back and organize these better, align on consistent coding style, remove dead code, etc. in separate patches later that will be easier to review. v2: - Add missing include in intel_pxp_irq.c v3: - Correct a few indentation errors (Lucas) - Minor conflict resolution Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Matt Roper authored
The various MI_PREDICATE registers have per-engine instances. Today we only utilize the RCS0 instance of each, but that will likely change in the future; switch to parameterized register definitions to make these easier to work with going forward. Of special note is MI_PREDICATE_RESULT_2; we only use it in one place in the driver today in HSW-specific code. It turns out that the bspec (page 94) lists two different offsets for this register on HSW; one is in the standard location shared by all other platforms (base + 0x3bc) and the other is an unusual location (0x2214). We're using the second, non-standard offset in i915 today; that offset doesn't exist on any other platforms (and it's not even 100% clear that it's correct for HSW) so I've renamed the current non-standard definition to HSW_MI_PREDICATE_RESULT_2; the new cross-platform parameterized macro (which is still unused at the moment) uses the standard offset. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Matt Roper authored
At the moment we only use R_PWR_CLK_STATE in the context of the RCS engine, but upcoming support for compute engines will start using instances relative to the CCS engine base offsets. Let's parameterize the register and move it to the engine reg header. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Matt Roper authored
Let's use 'struct i915_range' to express sets of b-counter and mux registers in the perf code. This makes the code more similar to how we handle things like multicast register ranges, forcewake tables, shadow tables, etc. and also lets us avoid needing symbolic register name definitions for the various range end points. With this change, many of the OA register definitions are no longer used in the code, so we can drop their #define's for simplicity. v2: Drop 'inline' from reg_in_range_table(). (Jani) v3: Split the first range in gen12_oa_mux_regs[] so that 0xd08 isn't whitelisted. (Umesh) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by:Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220127234334.4016964-3-matthew.d.roper@intel.com
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Matt Roper authored
The OA unit registers are only used by the perf code; move them to their own header file. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by:
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Jani Nikula authored
The only user of the VGA registers has switched to using the definitions in linux/vga.h, so these have become redundant. Remove them. Suggested-by:
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Jani Nikula authored
The video/vga.h has macros for the VGA registers. Switch to use them. v2: Use direct 0x01 instead of the confusing VGA_SEQ_CLOCK_MODE (Ville) Suggested-by:
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- 01 Feb, 2022 13 commits
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Ville Syrjälä authored
Use DISPLAY_VER rather than GRAPHICS_VER to determine availability of display hardware features. Signed-off-by:
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Ville Syrjälä authored
When reprogramming M/N live on BDW+ we must write the LINK_N register last as it's the one that arms the double buffered register update for all the M/N registers. Document this so that we don't accidentally break things. Signed-off-by:
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Ville Syrjälä authored
No point in special casing the check of dp_m2_n2 on pre-bdw platforms. Either the transcoder has M2/N2 in which case the values should be set to something sensible, or it doesn't in which case dp_m2_n2 is always zeroed. Signed-off-by:
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Ville Syrjälä authored
No point in special casing the dp_m2_n2 dumping. Just do it always. Signed-off-by:
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Ville Syrjälä authored
Program the PCH transcoder M2/N2 values appropriately. We're still missing a few things for PCH port DRRS but at least this means we can do readout/state check for dp_m2_n2 unconditionally. Signed-off-by:
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Ville Syrjälä authored
Make life simpler by always programming DP M2/N2 with a consistent value. This will lets use do state readout+chec unconditionally. I was first going to just set M2/N2=M1/N1 but then it occurred to me that it might interfere with fastboot on account of BIOS likely leaving the registers zeroed. So let's zero out the values instead (except TU where a zero register value actually means '1'). Still not sure that's the best approach but lets go with it for now. Signed-off-by:
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Ville Syrjälä authored
M2/N2 values are present for all ilk-ivb,vlv,chv (and hsw edp). Make the code reflect that. Signed-off-by:
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Ville Syrjälä authored
Pull the "can we do DRRS?" check into helper in order to reduce the clutter in intel_drrs_compute_config(). Signed-off-by:
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Ville Syrjälä authored
Currently we allow DRRS on IVB PCH ports, but we're missing a few programming steps meaning it is guaranteed to not work. And on HSW DRRS is not supported on anything but port A ever as only transcoder EDP has the M2/N2 registers (though I'm not sure if HSW ever has eDP on any other port). Starting from BDW all transcoders have the dynamically reprogrammable M/N registers so DRRS could work on any port. Stop initializing DRRS on ports where it cannot possibly work. Cc: stable@vger.kernel.org Signed-off-by:
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Ville Syrjälä authored
Follow the path laid out by hsw+ and extract helpers to configure the cpu transcoder for earlier platforms as well. Signed-off-by:
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Ville Syrjälä authored
Let's do the cpu transcoder M/N setup next to where we program most other cpu transcoder timings/etc. Signed-off-by:
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Ville Syrjälä authored
Do the PCH transcoder M/N setup next to where all the other PCH transcoder stuff is programmed. Matches the spec modeset sequence better. Signed-off-by:
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Ville Syrjälä authored
Instead of passing in the whole crtc state let's pass in just the bits of state we need. This will help with the DRRS code which shouldn't really be accessing the atomic state stuff directly as it gets called outside the normal atomic flows. v2: Fix set_m1_n1 vs. set_m2_n2 fumble for i9xx (Jani) Signed-off-by:
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