- 26 Apr, 2023 1 commit
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John Harrison authored
Dan Carpenter pointed out that 'err' was not being set in the case where the GuC firmware version range check fails. Fix that. Note that while this is a bug fix for a previous patch (see Fixes tag below). It is an exceedingly low risk bug. The range check is asserting that the GuC firmware version is within spec. So it should not be possible to ever have a firmware file that fails this check. If larger version numbers are required in the future, that would be a backwards breaking spec change and thus require a major version bump, in which case an old i915 driver would not load that new version anyway. Fixes: 9bbba066 ("drm/i915/guc: Use GuC submission API version number") Reported-by:
Dan Carpenter <error27@gmail.com> Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Cc: Andi Shyti <andi.shyti@linux.intel.com> Cc: Matthew Auld <matthew.auld@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230421224742.2357198-1-John.C.Harrison@Intel.com
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- 25 Apr, 2023 4 commits
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Tejas Upadhyay authored
WA 18018781329 is applicable now across all MTL steppings. V2: - Remove IS_MTL check, code already running for MTL - Matt Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
Tejas Upadhyay <tejas.upadhyay@intel.com> Reviewed-by:
Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by:
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Tejas Upadhyay authored
igt_live_test has pr_err dumped in case of some GT failures. It will be more informative regarding GT if we use gt_err instead. Cc: Andi Shyti <andi.shyti@intel.com> Signed-off-by:
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Fei Yang authored
This patch implements Wa_22016122933. In MTL, memory writes initiated by the Media tile update the whole cache line, even for partial writes. This creates a coherency problem for cacheable memory if both CPU and GPU are writing data to different locations within a single cache line. This patch circumvents the issue by making CPU/GPU shared memory uncacheable (WC on CPU side, and PAT index 2 for GPU). Additionally, it ensures that CPU writes are visible to the GPU with an intel_guc_write_barrier(). While fixing the CTB issue, we noticed some random GSC firmware loading failure because the share buffers are cacheable (WB) on CPU side but uncached on GPU side. To fix these issues we need to map such shared buffers as WC on CPU side. Since such allocations are not all done through GuC allocator, to avoid too many code changes, the i915_coherent_map_type() is now hard coded to return WC for MTL. v2: Simplify the commit message(Matt). BSpec: 45101 Signed-off-by:
Fei Yang <fei.yang@intel.com> Reviewed-by:
Nirmoy Das <nirmoy.das@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Fei Yang authored
PTE encode functions are platform dependent. This patch implements PTE functions for MTL, and ensures the correct PTE encode function is used by calling pte_encode function pointer instead of the hardcoded gen8 version of PTE encode. Fixes: b76c0dee ("drm/i915/mtl: Define MOCS and PAT tables for MTL") Signed-off-by:
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- 23 Apr, 2023 4 commits
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Andi Shyti authored
In the process of renaming all instances of 'dev_priv' to 'i915', start using 'i915' within the i915_drv.h file. Signed-off-by:
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Andi Shyti authored
for_each_engine() loops through engines in the GT, not in dev_priv. Because it's misleading, call it "gt__" instead of "dev_priv__". Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
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Fei Yang authored
Media GT has a different base for MOCS register, need to apply gsi_offset to the mmio address if not using the intel_uncore_r/w functions for register access. Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Madhumitha Tolakanahalli Pradeep authored
On MTL, GT can no longer allocate on LLC - only the CPU can. This, along with programming new register bits that MTL requires calls for a MOCS/PAT table update. Also the PAT index registers are multicasted for primary GT, and there is an address jump from index 7 to 8. This patch makes sure that these registers are programmed in the proper way. BSpec: 44509, 45101, 44235 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> Signed-off-by:
Aravind Iddamsetty <aravind.iddamsetty@intel.com> Signed-off-by:
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- 21 Apr, 2023 1 commit
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Fei Yang authored
On MTL, LLC is not shared between GT and CPU, set has_llc=0. Signed-off-by:
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- 20 Apr, 2023 1 commit
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Haridhar Kalvala authored
Workaround implementation to clear RDOP clock gating. Bspec: 66622 Signed-off-by:
Haridhar Kalvala <haridhar.kalvala@intel.com> Signed-off-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by:
Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230418220446.2205509-5-radhakrishna.sripada@intel.com
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- 19 Apr, 2023 4 commits
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Madhumitha Tolakanahalli Pradeep authored
Wa_22011802037 was being applied to all graphics_ver 11 & 12. This patch updates the if statement to apply the W/A to right platforms and extends it to MTL-M:A step. v1.1: Fix checkpatch warning. v2: Change the check to reflect the wa at other places(Lucas) Bspec: 66622 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Signed-off-by:
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Tejas Upadhyay authored
In order to enable complete multi-GT, loop through all the GTs, rather than relying on the to_gt(), which only provides a reference to the primary GT. Problem appear when it runs on platform like MTL where different set of engines are possible on different GTs. Signed-off-by:
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Tejas Upadhyay authored
In order to enable complete multi-GT, use the GT reference obtained directly from the engine, rather than relying on the to_gt(), which only provides a reference to the primary GT. Problem appear when it runs on platform like MTL where different set of engines are possible on different GTs. Signed-off-by:
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Tejas Upadhyay authored
In order to enable complete multi-GT, use the GT reference obtained directly from the engine, rather than relying on the to_gt(), which only provides a reference to the primary GT. Problem appear when it runs on platform like MTL where different set of engines are possible on different GTs. Cc: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by:
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- 18 Apr, 2023 1 commit
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Andi Shyti authored
In multi-gt systems IRQs need to be reset and enabled per GT. This might add some redundancy when handling interrupts for engines that might not exist in every tile, but helps to keep the code cleaner and more understandable. Signed-off-by:
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- 15 Apr, 2023 1 commit
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Cong Liu authored
This patch fixes memory leaks on error escapes in function fake_get_pages Fixes: c3bfba9a ("drm/i915: Check for integer truncation on scatterlist creation") Signed-off-by:
Cong Liu <liucong2@kylinos.cn> Reviewed-by:
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- 14 Apr, 2023 1 commit
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Lucas De Marchi authored
When HuC is loaded by GSC, there is no header definition for the kernel to look at and firmware is just handed to GSC. However when reading the version, it should still check the size of the blob to guarantee it's not incurring into out-of-bounds array access. If firmware is smaller than expected, the following message is now printed: # echo boom > /lib/firmware/i915/dg2_huc_gsc.bin # dmesg | grep -i huc [drm] GT0: HuC firmware i915/dg2_huc_gsc.bin: invalid size: 5 < 184 [drm] *ERROR* GT0: HuC firmware i915/dg2_huc_gsc.bin: fetch failed -ENODATA ... Even without this change the size, header and signature are still checked by GSC when loading, so this only avoids the out-of-bounds array access. Fixes: a7b516bd ("drm/i915/huc: Add fetch support for gsc-loaded HuC binary") Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230413200349.3492571-1-lucas.demarchi@intel.com
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- 11 Apr, 2023 5 commits
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Nirmoy Das authored
Stolen memory is not usable for MTL A0 stepping beyond certain access size and we have no control over userspace access size of /dev/fb which can be backed by stolen memory. So disable stolen memory backed fb by setting i915->dsm.usable_size to zero. v2: remove hsdes reference and fix commit message(Andi) v3: use revid as we want to target SOC stepping(Radhakrishna) Cc: Matthew Auld <matthew.auld@intel.com> Cc: Andi Shyti <andi.shyti@linux.intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
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Joonas Lahtinen authored
Need to pull in commit from drm-next (earlier in drm-intel-next): 1eca0778 ("drm/i915: add struct i915_dsm to wrap dsm members together") In order to merge following patch to drm-intel-gt-next: https://patchwork.freedesktop.org/patch/530942/?series=114925&rev=6Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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Daniel Vetter authored
Merge tag 'mediatek-drm-next-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next Mediatek DRM Next for Linux 6.4 1. Add support for 10-bit overlays 2. Add MediaTek SoC DRM (vdosys1) support for mt8195 3. Change mmsys compatible for mt8195 mediatek-drm 4. Only trigger DRM HPD events if bridge is attached 5. Change the aux retries times when receiving AUX_DEFER Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> From: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230410233005.2572-1-chunkuang.hu@kernel.org
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https://gitlab.freedesktop.org/drm/msmDaniel Vetter authored
main pull request for v6.4 Core Display: ============ * Bugfixes for error handling during probe * rework UBWC decoder programming * prepare_commit cleanup * bindings for SM8550 (MDSS, DPU), SM8450 (DP) * timeout calculation fixup * atomic: use drm_crtc_next_vblank_start() instead of our own custom thing to calculate the start of next vblank DP: == * interrupts cleanup DPU: === * DSPP sub-block flush on sc7280 * support AR30 in addition to XR30 format * Allow using REC_0 and REC_1 to handle wide (4k) RGB planes * Split the HW catalog into individual per-SoC files DSI: === * rework DSI instance ID detection on obscure platforms GPU: === * uapi C++ compatibility fix * a6xx: More robust gdsc reset * a3xx and a4xx devfreq support * update generated headers * various cleanups and fixes * GPU and GEM updates to avoid allocations which could trigger reclaim (shrinker) in fence signaling path * dma-fence deadline hint support and wait-boost * a640 speedbin support * a650 speedbin support Conflicts in drivers/gpu/drm/msm/adreno/adreno_gpu.c: Conflict between the 7fa5047a ("drm: Use of_property_present() for testing DT property presence") and 9f251f93 ("drm/msm/adreno: Use OPP for every GPU generation"). The latter removed the of_ function call outright, so I went with what's in the PR unchanged. From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvwuj5tabyW910+N-B=5kFNAC7QNYoQ=0xi3roBjQvFFQ@mail.gmail.comSigned-off-by:
Daniel Vetter <daniel.vetter@intel.com>
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Daniel Vetter authored
Merge tag 'drm-habanalabs-next-2023-04-10' of https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/linux into drm-next This tag contains additional habanalabs driver changes for v6.4: - uAPI changes: - Add a definition of a new Gaudi2 server type. This is used by userspace to know what is the connectivity between the accelerators inside the server - New features and improvements: - speedup h/w queues test in Gaudi2 to reduce device initialization times. - Firmware related fixes: - Fixes to the handshake protocol during f/w initialization. - Sync f/w events interrupt in hard reset to avoid warning message. - Improvements to extraction of the firmware version. - Misc bug fixes and code cleanups. Notable fixes are: - Multiple fixes for interrupt handling in Gaudi2. - Unmap mapped memory in case TLB invalidation fails. Signed-off-by:
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- 08 Apr, 2023 17 commits
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Tomer Tayar authored
hl_sysfs_fini() is called only if hl_sysfs_init() completes successfully. Therefore if hl_sysfs_init() fails, need to remove any sysfs group that was added until that point. Signed-off-by:
Tomer Tayar <ttayar@habana.ai> Reviewed-by:
Oded Gabbay <ogabbay@kernel.org> Signed-off-by:
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Moti Haimovski authored
HW queues testing at driver load and after reset takes a substantial amount of time. This commit reduces the queues test time in Gaudi2 devices by running all the tests in parallel instead of one after the other. Time measurements on tests duration shows that the new method is almost x100 faster than the serial approach. Signed-off-by:
Moti Haimovski <mhaimovski@habana.ai> Reviewed-by:
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Dani Liberman authored
There is only single eq entry for arc farm sei event which aggregates events from the four arc farms. Fix the code to handle this event according to this behavior. Signed-off-by:
Dani Liberman <dliberman@habana.ai> Reviewed-by:
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Ofir Bitton authored
Multi MSI interrupts aren't working in Gaudi1 and because of that, we are only using a single MSI interrupt. Therefore, let's remove this dead code in order to avoid confusion. Signed-off-by:
Ofir Bitton <obitton@habana.ai> Reviewed-by:
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Oded Gabbay authored
Add definition of a new Gaudi2 server type. This represents the connectivity between the cards in that server type. Signed-off-by:
Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com>
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Ofir Bitton authored
Removing redundant asic prop variable as we don't need to expose this to common code. In addition, fix some typos. Signed-off-by:
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Koby Elbaz authored
Sending COMMS_GOTO_WFE instructs the FW's CPU to halt (WFE state). Once sent, FW's CPU isn't expected to continue communicating with LKD. Therefore, the stage of waiting for COMMS_STS_OK should be skipped or else waiting for COMMS_STS_OK will simply timeout, which will trigger unexpected behavior. Signed-off-by:
Koby Elbaz <kelbaz@habana.ai> Reviewed-by:
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Tal Cohen authored
Receiving events from FW, while the device is in hard reset, causes a warning message in Driver log. The message may point to a problem in the Driver or FW. But It also can appear as a result of events that have been sent from FW just before the hard reset. In order to avoid receiving events from FW while the device is in reset and is already in 'disabled' mode, sync the f/w events interrupt right before setting the device to 'disabled'. Signed-off-by:
Tal Cohen <talcohen@habana.ai> Reviewed-by:
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Ofir Bitton authored
During event handling, driver sets relevant reset and user event notifier flags. Fix few wrong flags settings. Signed-off-by:
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Tomer Tayar authored
The decoder IRQ status register may have several set bits upon an abnormal interrupt. Therefore, when setting the events mask, need to check all bits and not using if-else. Signed-off-by:
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Tomer Tayar authored
Decoder abnormal interrupts are for errors and not for completion, so rename the relevant work and work function to not include 'completion'. Signed-off-by:
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Ofir Bitton authored
There are rare cases of failures when cards are initialized due to wrong values in efuse mappings that are parsed by firmware. To help debug those cases, print (in debug level) the raw binning masks as fetched from the firmware during device initialization. Signed-off-by:
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Ofir Bitton authored
Current mapping between HMMU event and HMMU block is wrong. In addition the captured address in case of a page fault or an access error is scrambled, Hence we must call the descramble function. Signed-off-by:
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Dafna Hirschfeld authored
1. Rename the func to hl_get_preboot_major_minor because we also set the extracted values in hdev fields. 2. Free the allocated string in the calling function which makes more sense Signed-off-by:
Dafna Hirschfeld <dhirschfeld@habana.ai> Reviewed-by:
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Dani Liberman authored
The register which needs to be cleared is the valid register instead of the address. Signed-off-by:
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Tal Cohen authored
Fix an issue in hard reset flow in which the driver didn't send a disable pci message if there was an active compute context. In hard reset, disable pci message should be sent no matter if a compute context exists or not. Signed-off-by:
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Tal Cohen authored
The disable pci message is sent in reset device. It informs the FW not to raise more EQs. The Driver may ignore received EQs, when the device is in disabled mode. The duplication happens when hard reset is scheduled during compute reset and also performs 'escalate_reset_flow'. Signed-off-by:
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