1. 24 Sep, 2014 3 commits
    • Santosh Shilimkar's avatar
      Documentation: dt: soc: add Keystone Navigator DMA bindings · 8172296d
      Santosh Shilimkar authored
      The Keystone Navigator DMA driver sets up the dma channels and flows for
      the QMSS(Queue Manager SubSystem) who triggers the actual data movements
      across clients using destination queues. Every client modules like
      NETCP(Network Coprocessor), SRIO(Serial Rapid IO) and CRYPTO
      Engines has its own instance of packet dma hardware. QMSS has also
      an internal packet DMA module which is used as an infrastructure
      DMA with zero copy.
      
      Initially this driver was proposed as DMA engine driver but since the
      hardware is not typical DMA engine and hence doesn't comply with typical
      DMA engine driver needs, that approach was naked. Link to that
      discussion -
      	https://lkml.org/lkml/2014/3/18/340
      
      As aligned, now we pair the Navigator DMA with its companion Navigator
      QMSS subsystem driver.
      
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Kumar Gala <galak@codeaurora.org>
      Cc: Olof Johansson <olof@lixom.net>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarSandeep Nair <sandeep_n@ti.com>
      Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
      8172296d
    • Sandeep Nair's avatar
      soc: ti: add Keystone Navigator QMSS driver · 41f93af9
      Sandeep Nair authored
      The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
      the main hardware sub system which forms the backbone of the Keystone
      Multi-core Navigator. QMSS consist of queue managers, packed-data structure
      processors(PDSP), linking RAM, descriptor pools and infrastructure
      Packet DMA.
      
      The Queue Manager is a hardware module that is responsible for accelerating
      management of the packet queues. Packets are queued/de-queued by writing or
      reading descriptor address to a particular memory mapped location. The PDSPs
      perform QMSS related functions like accumulation, QoS, or event management.
      Linking RAM registers are used to link the descriptors which are stored in
      descriptor RAM. Descriptor RAM is configurable as internal or external memory.
      
      The QMSS driver manages the PDSP setups, linking RAM regions,
      queue pool management (allocation, push, pop and notify) and descriptor
      pool management. The specifics on the device tree bindings for
      QMSS can be found in:
      	Documentation/devicetree/bindings/soc/keystone-navigator-qmss.txt
      
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Kumar Gala <galak@codeaurora.org>
      Cc: Olof Johansson <olof@lixom.net>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarSandeep Nair <sandeep_n@ti.com>
      Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
      41f93af9
    • Sandeep Nair's avatar
      Documentation: dt: soc: add Keystone Navigator QMSS bindings · a4dfb8c4
      Sandeep Nair authored
      The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
      the main hardware sub system which forms the backbone of the Keystone
      Multi-core Navigator. QMSS consist of queue managers, packed-data structure
      processors(PDSP), linking RAM, descriptor pools and infrastructure
      Packet DMA.
      
      The Queue Manager is a hardware module that is responsible for accelerating
      management of the packet queues. Packets are queued/de-queued by writing or
      reading descriptor address to a particular memory mapped location. The PDSPs
      perform QMSS related functions like accumulation, QoS, or event management.
      Linking RAM registers are used to link the descriptors which are stored in
      descriptor RAM. Descriptor RAM is configurable as internal or external memory.
      
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Kumar Gala <galak@codeaurora.org>
      Cc: Olof Johansson <olof@lixom.net>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarSandeep Nair <sandeep_n@ti.com>
      Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
      a4dfb8c4
  2. 16 Aug, 2014 37 commits