- 26 May, 2023 7 commits
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Kathiravan T authored
480MHz is derived from P_GPLL4_OUT_AUX not from P_GPLL4_OUT_MAIN. Update the freq_tbl with the correct src. Fixes: 3d89d529 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Reported-by:
Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Signed-off-by:
Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230417044342.9406-1-quic_kathirav@quicinc.com
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Konrad Dybcio authored
GPLL0_OUT_DIV (.fw_name = "gcc_disp_gpll0_div_clk_src") was previously made to reuse the same parent enum entry as GPLL0_OUT_MAIN (.fw_name = "gcc_disp_gpll0_clk_src") in parent_map_2. Resolve it by introducing its own entry in the parent enum and correctly assigning it in disp_cc_parent_map_2[]. Fixes: cc517ea3 ("clk: qcom: Add display clock controller driver for QCM2290") Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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Konrad Dybcio authored
BI_TCXO_AO (.fw_name = "bi_tcxo_ao") was previously made to reuse the same parent enum entry as BI_TCXO (.fw_name = "bi_tcxo") in parent_map_2. Resolve it by introducing its own entry in the parent enum and correctly assigning it in disp_cc_parent_map_2[]. Fixes: cc517ea3 ("clk: qcom: Add display clock controller driver for QCM2290") Signed-off-by:
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Robert Marko authored
Networking resets in IPQ6018 all use bitmask as they require multiple bits to be set and cleared instead of a single bit. So, current networking resets have the same register and bit 0 set which is clearly incorrect. Fixes: d9db07f0 ("clk: qcom: Add ipq6018 Global Clock Controller support") Signed-off-by:
Robert Marko <robimarko@gmail.com> Signed-off-by:
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Robert Marko authored
Update the UBI32 alpha PLL config to the latest values from the downstream QCA 5.4 kernel. Signed-off-by:
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Devi Priya authored
Add the compatible and configuration values for A73 Huayra PLL found on IPQ9574. Co-developed-by:
Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by:
Devi Priya <quic_devipriy@quicinc.com> Acked-by:
Stephen Boyd <sboyd@kernel.org> Reviewed-by:
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Devi Priya authored
IPQ9574 uses A73 PLL of type Huayra. Add the IPQ9574 A73 compatible to A53 bindings as the PLL properties match with that of A53. Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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- 25 May, 2023 32 commits
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Krzysztof Kozlowski authored
The GCC clock controller needs CX power domain, at least according to DTS: sc7280-herobrine-crd-pro.dtb: clock-controller@100000: Unevaluated properties are not allowed ('power-domains' was unexpected) Acked-by:Rob Herring <robh@kernel.org> Signed-off-by:
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Krzysztof Kozlowski authored
The GCC clock controller needs CX power domain, at least according to DTS: sc7180-trogdor-pompom-r3.dtb: clock-controller@100000: Unevaluated properties are not allowed ('power-domains' was unexpected) Acked-by: -
Krzysztof Kozlowski authored
The initial SM8250 GCC driver added in commit 3e577092 ("clk: qcom: gcc: Add global clock controller driver for SM8250") already consumed it on the clock. This fixes warnings like: sm8250-xiaomi-elish-csot.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk'] is too long Fixes: 98394efb ("dt-bindings: clock: Add SM8250 GCC clock bindings") Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
There is no point to allow selecting clock controller drivers for Qualcomm ARMv7 SoCs when building ARM64 kernel, and vice versa. This makes kernel configuration more difficult as many do not remember the Qualcomm SoCs model names/numbers. No features should be lost because: 1. There won't be a single image for ARMv7 and ARMv8/9 SoCs. 2. Newer ARMv8/9 SoCs won't be running in arm32 emulation mode. Signed-off-by:
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Imran Shaik authored
Add Global Clock Controller (GCC) support for SDX75 platform. Signed-off-by:
Imran Shaik <quic_imrashai@quicinc.com> Signed-off-by:
Taniya Das <quic_tdas@quicinc.com> Signed-off-by:
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Imran Shaik authored
Add support for RPMH clocks for SDX75 platform. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Imran Shaik authored
Add compatible string for qcom RPMHCC for SDX75 platform. Signed-off-by:
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Imran Shaik authored
Add support to handle the invert logic for branch2 clocks. Invert branch halt would indicate the clock ON when CLK_OFF bit is '1' and OFF when CLK_OFF bit is '0'. Signed-off-by:
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Bjorn Andersson authored
Merge SDX75 Global Clock Controller DeviceTree binding through a topic branch, to allow inclusion in DeviceTree source as well.
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Luca Weiss authored
On older platforms like msm8226, msm8974 and msm8916 the driver in the downstream kernel enables scaling first before doing the handover of the clocks. While this normally doesn't seem to cause noticeable problems, on apq8026-asus-sparrow this causes the device to immediately reboot, perhaps due to older rpm firmware that becomes unhappy. On newer platforms the order has swapped and enabling scaling is done after the handover, so let's introduce this behavior only conditionally for msm8226 and msm8974 for now. Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Reviewed-by:
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Christian Marangi authored
The same exact F frequency table entry is defined in clk-rcg.h Drop the redundant define to cleanup code. Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Reviewed-by:
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Christian Marangi authored
The same exact F frequency table entry is defined in clk-rcg.h Drop the redundant define to cleanup code. Signed-off-by:
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Krzysztof Kozlowski authored
The Qualcomm MSM8953 GCC clock controller has clock inputs, thus existing gcc-other.yaml was not describing it fully. Move the binding to its own schema file and document the clocks based on DTS. Add driver contributors as its maintainers. Signed-off-by:
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Konrad Dybcio authored
The vast majority of shared RCGs were not marked as such. Fix it. Fixes: 496d1a13 ("clk: qcom: Add Global Clock Controller driver for QCM2290") Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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Jagadeesh Kona authored
Add support for the video clock controller for video clients to be able to request for videocc clocks on SM8550 platform. Co-developed-by:
Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by:
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Jagadeesh Kona authored
Add compatible string for SM8550 video clock controller. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Jagadeesh Kona authored
The lucid ole pll reuses lucid evo ops but it has an additional test control register which is required to be programmed, add support to program the same. Signed-off-by:
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Taniya Das authored
Add support for the video clock controller driver for peripheral clock clients to be able to request for video cc clocks. Signed-off-by:
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Bjorn Andersson authored
Merge the SM8450 Video Clock Controller DeviceTree binding through a topic branch, in order to be able to use the introduced constants in changes on DeviceTree source branch as well.
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Konrad Dybcio authored
Add support for the Video Clock Controller found on the SM8350 SoC. Reviewed-by:
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Bjorn Andersson authored
Merge the Video Clock Controller DeviceTree bindings through a topic branch, in order to be able to use the introduced constants in the DeviceTree source branch as well.
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Konrad Dybcio authored
SM8350, like most recent higher-end chips has a separate clock controller block just for the Venus IP. Document it. The binding was separated as the driver, unlike the earlier ones, doesn't expect clock-names to keep it easier to maintain. Signed-off-by:
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Taniya Das authored
Add device tree bindings for the video clock controller on Qualcomm SM8450 platform. Signed-off-by:
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Imran Shaik authored
Add support for qcom global clock controller bindings for SDX75 platform. Signed-off-by:
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Mantas Pucka authored
SDCC clocks must be rounded down to avoid overclocking the controller. Fixes: d9db07f0 ("clk: qcom: Add ipq6018 Global Clock Controller support") Signed-off-by:
Mantas Pucka <mantas@8devices.com> Reviewed-by:
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Konrad Dybcio authored
We should never let go of the active-only XO vote, as otherwise the RPM may decide that there are no online users and it can be shut down, resulting in a total, uncontrolled system collapse. Guarantee this through adding the CLK_IS_CRITICAL flag. Signed-off-by:
Matti Lehtimäki <matti.lehtimaki@gmail.com> Signed-off-by:
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Konrad Dybcio authored
In preparation for supporting keepalive clocks which can never be shut off (as the platform would fall apart otherwise), make the DEFINE_CLK_SMD_RPM_BRANCH_A macro accept clock flags for the active-only clock. Signed-off-by:
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Konrad Dybcio authored
In preparation for supporting keepalive clocks which can never be shut off (as the platform would fall apart otherwise), make the __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX macro accept clock flags for the active-only clock. Signed-off-by:
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Konrad Dybcio authored
For no apparent reason (as there's just one RPM per SoC), all clocks currently store a copy of a pointer to smd_rpm. Introduce a single, global one to save up on space in each clk definition. bloat-o-meter reports: Total: Before=41887, After=40843, chg -2.49% Signed-off-by:
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Taniya Das authored
Camera titan top GDSC is a parent supply to all other camera GDSCs. Titan top GDSC is required to be enabled before enabling any other camera GDSCs and it should be disabled only after all other camera GDSCs are disabled. Ensure this behavior by marking titan top GDSC as parent of all other camera GDSCs. Fixes: 15d09e83 ("clk: qcom: camcc: Add camera clock controller driver for SC7180") Signed-off-by:
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Dmitry Baryshkov authored
After the internal discussions, it looks like this clock is managed by RPM itself. Linux kernel should not touch it on its own, as this causes disagreement with RPM. Shutting down this clock causes the OCMEM<->GPU interface to stop working, resulting in GPU hangchecks/timeouts. Fixes: d8b21201 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)") Suggested-by:
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Kathiravan T authored
SDCC clocks must be rounded down to avoid overclocking the controller. Fixes: 3d89d529 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Signed-off-by:
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- 23 May, 2023 1 commit
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Bjorn Andersson authored
In many designs the power-domains provided by the GPU clock controller are powered by some GFX rail, add power-domains as a valid property to allow this to be specified. Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Acked-by:
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