- 21 May, 2009 17 commits
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Kumar Gala authored
We shouldn't directly access sysdata to get the pci_controller. Instead use pci_bus_to_host() for this purpose. In the future we might have sysdata be a device_node to match ppc64 and unify the code between ppc32 & ppc64. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Kumar Gala authored
We shouldn't directly access sysdata to get the pci_controller. Instead use pci_bus_to_host() for this purpose. In the future we might have sysdata be a device_node to match ppc64 and unify the code between ppc32 & ppc64. Signed-off-by:
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Milton Miller authored
This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards compatibilty for CPUs before 2.06. Only useful for bare metal systems. Signed-off-by:
Milton Miller <miltonm@bga.com> Signed-off-by:
Michael Neuling <mikey@neuling.org> Signed-off-by:
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Milton Miller authored
powerpc: Enable MMU feature sections for inline asm This adds the ability to do MMU feature sections for inline asm. Signed-off-by:
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Michael Neuling authored
Cleans up the VSX load/store instructions by moving them into ppc-opcode.h. Signed-off-by:
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Michael Neuling authored
Make macros more braces happy. Signed-off-by:
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Kumar Gala authored
We believe if a toolchain supports PT_GNU_STACK that it sets the proper PHDR permissions. Therefor elf_read_implies_exec() should only be true if we don't see PT_GNU_STACK set. Signed-off-by:
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Michael Ellerman authored
So select GENERIC_HARDIRQS_NO__DO_IRQ to disable it. Signed-off-by:
Michael Ellerman <michael@ellerman.id.au> Signed-off-by:
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Michael Ellerman authored
Don't call __do_IRQ() directly in gatwick_action(), use generic_handle_irq(). Signed-off-by:
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Michael Ellerman authored
We should no longer have any irq code that needs __do_IRQ(), so remove the fallback to __do_IRQ(). Signed-off-by:
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Michael Ellerman authored
The guts of do_IRQ() isn't really the right place to be documenting the ppc_md.get_irq() interface. So move the comment into machdep.h Signed-off-by:
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Michael Ellerman authored
Makes do_IRQ() shorter and clearer. Signed-off-by:
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Michael Ellerman authored
Rather than a giant ifdef in the body of do_IRQ(), including a dangling else, move the irq stack logic into a separate routine and do the ifdef there. Signed-off-by:
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Geoff Levand authored
ps3 has 4 ipis per cpu and can use the new smp_request_message_ipi to reduce path length when receiving an ipi. This has the side effect of setting IRQF_PERCPU. Signed-off-by:
Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by:
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Robert Jennings authored
Adds support for the "unused" page hint which can be used in shared memory partitions to flag pages not in use, which will then be stolen before active pages by the hypervisor when memory needs to be moved to LPARs in need of additional memory. Failure to mark pages as 'unused' makes the LPAR slower to give up unused memory to other partitions. This adds the kernel parameter 'cmo_free_hint' to disable this functionality. Signed-off-by:
Brian King <brking@linux.vnet.ibm.com> Signed-off-by:
Robert Jennings <rcj@linux.vnet.ibm.com> Signed-off-by:
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Tony Breeds authored
mpic_find() was overloaded to do two things, finding the mpic instance for a given interrupt and returning if it's an IPI. Instead we introduce mpic_is_ipi() and simplify mpic_find() to just return the mpic instance Also silences the warning: arch/powerpc/sysdev/mpic.c: In function 'mpic_irq_set_priority': arch/powerpc/sysdev/mpic.c:1382: warning: 'is_ipi' may be used uninitialized in this function Signed-off-by:
Tony Breeds <tony@bakeyournoodle.com> Acked-by:
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Sean MacLennan authored
Now that leds-gpio is a proper OF platform driver, the Warp can use the leds-gpio driver rather than the old out-of-kernel driver. One side-effect is the leds-gpio driver always turns the leds off while the old driver left them alone. So we have to set them back to the correct settings. Signed-off-by:
Sean MacLennan <smaclennan@pikatech.com> Signed-off-by:
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- 19 May, 2009 23 commits
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Kumar Gala authored
Previouslly we just always set the inbound window to 2G. This was broken for systems with >2G. If a system has >=4G we will need SWIOTLB support to handle that case. We now allocate PCICSRBAR/PEXCSRBAR right below the lowest PCI outbound address for MMIO or the 4G boundary (if the lowest PCI address is above 4G). Signed-off-by: -
Kumar Gala authored
The P2020 is a dual e500v2 core based SOC with: * 3 PCIe controllers * 2 General purpose DMA controllers * 2 sRIO controllers * 3 eTSECS * USB 2.0 * SDHC * SPI, I2C, DUART * enhanced localbus * and optional Security (P2020E) security w/XOR acceleration The p2020 DS reference board is pretty similar to the existing MPC85xx DS boards and has a ULI 1575 connected on one of the PCIe controllers. Signed-off-by:
Ted Peters <Ted.Peters@freescale.com> Signed-off-by:
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Kumar Gala authored
Updated the binding spec to use "fsl,eshdc" as the base compatible rather than the first chip in the family. Signed-off-by: -
Li Yang authored
Signed-off-by:
Li Yang <leoli@freescale.com> Signed-off-by:
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Li Yang authored
Instead of fixed address in old code. Signed-off-by:
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Kumar Gala authored
We we build with resource_size_t as a 64-bit quantity we get: arch/powerpc/sysdev/fsl_rio.c: In function 'fsl_rio_setup': arch/powerpc/sysdev/fsl_rio.c:1029: warning: format '%08x' expects type 'unsigned int', but argument 4 has type 'resource_size_t' arch/powerpc/sysdev/fsl_rio.c:1029: warning: format '%08x' expects type 'unsigned int', but argument 5 has type 'resource_size_t' Signed-off-by: -
Kumar Gala authored
In these configuration we expect to have large amounts of memory (> 4G) and thus will bounce via swiotlb some region of PCI address space. The outbound windows were wasting 512M of address space by leaving a gap between the top of the outbound window and the 4G boundary. By moving the top of the outbound window up to the 4G boundary we can reclaim the vast majority of the 512M (minus space needed for PEXCSRBAR) and thus reduces the amount of memory we have to bounce. Signed-off-by: -
Kumar Gala authored
Its feasible based on how the PCI address map is setup that the region of PCI address space used for MSIs differs for each PHB on the same SoC. Instead of assuming that the address mappes to CCSRBAR 1:1 we read PEXCSRBAR (BAR0) for the PHB that the given pci_dev is on. Signed-off-by: -
Kumar Gala authored
The MPC8568/9 chips support MSIs on PCIe so no reason not to enable them. Signed-off-by: -
Kumar Gala authored
We we build with dma_addr_t as a 64-bit quantity we get: drivers/dma/fsldma.c: In function 'fsl_chan_xfer_ld_queue': drivers/dma/fsldma.c:625: warning: cast to pointer from integer of different size drivers/dma/fsldma.c: In function 'fsl_dma_chan_do_interrupt': drivers/dma/fsldma.c:737: warning: cast to pointer from integer of different size drivers/dma/fsldma.c:737: warning: cast to pointer from integer of different size drivers/dma/fsldma.c: In function 'of_fsl_dma_probe': drivers/dma/fsldma.c:927: warning: cast to pointer from integer of different Signed-off-by:
Dan Williams <dan.j.williams@intel.com>
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Anton Vorontsov authored
For serial flash support we need to: - Add QE Par IO Bank E device tree node, a GPIO from this bank is used for SPI chip-select line; - Add serial-flash node; - Add proper module alias into of/base.c. Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by:
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Anton Vorontsov authored
Select HAS_RAPIDIO symbol and add rio nodes for MPC8568E-MDS and MPC8569E-MDS boards. Signed-off-by:
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Anton Vorontsov authored
Note that eSDHC and DUART0 are mutually exclusive on MPC8569E-MDS boards. Default option is DUART0, so eSDHC is disabled by default. U-Boot will fixup device tree if eSDHC should be used instead of DUART0. Signed-off-by:
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Anton Vorontsov authored
This patch fixes bogus reg = <> property in the localbus node, and fixes interrupt property (should be "interrupts"). Also add node for NAND support. Signed-off-by:
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Anton Vorontsov authored
fsl,exec-units-mask should be 0xbfe to include SNOW unit in MPC8569E's security engine. Signed-off-by:
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Anton Vorontsov authored
This patch adds PCI IDs for MPC8569 and MPC8569E processors, plus adds appropriate quirks for these IDs, and thus makes PCI-E actually work on MPC8569E-MDS boards. Signed-off-by:
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Kumar Gala authored
Between the addition of the ecm/mcm law nodes and the fact that the get_immrbase() has been using the range property of the SoC to determine the base address of CCSR space we no longer need the reg property at the soc node level. It has been ill specified and varied between device trees to cover either the {e,m}cm-law node, some odd subset of CCSR space or all of CCSR space. Signed-off-by: -
Haiying Wang authored
Add fsl,qe-num-riscs and fsl,qe-num-snums to all the devices trees which have qe node. Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by:
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Haiying Wang authored
The MPC8569 is similiar to the MPC8568. It doubles the number of QUICC Engine RISC cores from 2 to 4. Removes eTSECs, TLU and adds the eSDHC controller. Signed-off-by:
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Haiying Wang authored
In the case the QE has 46 SNUMs for the threads to support four UCC Ethernet at 1000Base-T simultaneously. Signed-off-by:
David S. Miller <davem@davemloft.net> Acked-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
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Haiying Wang authored
The latest QE chip may have more Serial Number(SNUM)s of thread to use. We will get the number of SNUMs from device tree by reading the new property "fsl,qe-num-snums", and set 28 as the default number of SNUMs so that it is compatible with the old QE chips' device trees which don't have this new property. The macro QE_NUM_OF_SNUM is defined as the maximum number in QE snum table which is 256. Also we update the snum_init[] array with 18 more new SNUMs which are confirmed to be useful on new chip. Signed-off-by:
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Haiying Wang authored
Change the definition of riscTx and riscRx to unsigned integer instead of enum, and change their values to support 4 risc allocation if the qe has 4 RISC engines. Signed-off-by:
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Haiying Wang authored
Change the RISC allocation to macros instead of enum, add function to read the number of risc engines from the new property "fsl,qe-num-riscs" under the qe node in dts. Add new property "fsl,qe-num-riscs" description in qe.txt Signed-off-by:
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