1. 17 Mar, 2010 1 commit
    • Clemens Ladisch's avatar
      firewire: ohci: add cycle timer quirk for the TI TSB12LV22 · 8301b91b
      Clemens Ladisch authored
      Among the many entries in the TSB12LV22 errata list (TI literature
      number SLLS312) is the following:
      
        PCI Slave reads of the Cycle Timer register may occasionally get an
        incorrect value.
        Software may be able to validate value by reading the register
        multiple times rapidly and evaluating for a reasonable difference.
      
      Signed-off-by: Clemens Ladisch <clemens@ladisch.de> (untested)
      Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de> (added #define)
      8301b91b
  2. 15 Mar, 2010 1 commit
  3. 24 Feb, 2010 29 commits
  4. 23 Feb, 2010 9 commits