- 20 Feb, 2020 21 commits
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Matt Roper authored
It wasn't terribly clear from the bspec's wording, but after discussion with the hardware folks, it turns out that we need to preserve the pre-existing contents of the MBUS ABOX control register when initializing a few specific bits. Bspec: 49213 Bspec: 50096 Fixes: 4cb4585e ("drm/i915/icl: initialize MBus during display init") Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200204011032.582737-1-matthew.d.roper@intel.comReviewed-by:
Matt Atwood <matthew.s.atwood@intel.com>
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Ville Syrjälä authored
We have to write quite a few registers when programming the pipe scaler. Let's use intel_de_write_fw() for these to reduce the lockdep overhead a bit. All plane registers (including plane scaler) already do this. We already had a few accidental intel_de_write_fw() in there. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200212161738.28141-3-ville.syrjala@linux.intel.comReviewed-by:
Jani Nikula <jani.nikula@intel.com>
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Ville Syrjälä authored
Make the PFIT_PIPE stuff less ugly via parametrization. Signed-off-by:
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Ville Syrjälä authored
Currently we only set the DRM_CONNECTOR_POLL_{DISCONNECT,CONNECT} bits in intel_connector->polled (the base setting), leading to some confusing looking code to reset drm_connector->polled (the actual setting) to DRM_CONNECTOR_POLL_HPD. Let's set intel_connector->polled = DRM_CONNECTOR_POLL_HPD for all hpd capable connectors, and then we don't need so many special cases in the hotplug code. Signed-off-by: -
Ville Syrjälä authored
No point in looping over all connectors for each hpd pin. Just loop over each connector first and deal with each one's hpd pin. Then loop over all the hpd pins to mark them as enabled again. Signed-off-by:
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Ville Syrjälä authored
We have a nice little helper to compute a single LUT entry for everything except the 8bpc legacy gamma mode. Let's complete the set. Signed-off-by:
Emil Velikov <emil.velikov@collabora.com>
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Daniele Ceraolo Spurio authored
We are quite trigger happy in cleaning up the firmware blobs, as we do so from several error/fini paths in GuC/HuC/uC code. We do have the __uc_cleanup_firmwares cleanup function, which unwinds __uc_fetch_firmwares and is already called both from the error path of gem_init and from gem_driver_release, so let's stop cleaning up from all the other paths. The fact that we're not cleaning the firmware immediately means that we can't consider firmware availability as an indication of initialization success. A "LOADABLE" status has been added to indicate that the initialization was successful, to be used to selectively load HuC only if HuC init has completed (HuC init failure is not considered a fatal error). v2: s/ready_to_load/loadable (Michal), only run guc/huc_fini if the fw is in loadable state Signed-off-by:Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> #v1 Reviewed-by:
John Harrison <John.C.Harrison@Intel.com> Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200218223327.11058-9-daniele.ceraolospurio@intel.com
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Daniele Ceraolo Spurio authored
Now that we can differentiate wants vs uses GuC/HuC, intel_uc_init is restricted to running only if we have successfully fetched the required blob(s) and are committed to using the microcontroller(s). The only remaining thing that can go wrong in uc_init is the allocation of GuC/HuC related objects; if we get such a failure better to bail out immediately instead of wedging later, like we do for e.g. intel_engines_init, since without objects we can't use the HW, including not being able to attempt the firmware load. While at it, remove the unneeded fw_cleanup call (this is handled outside of gt_init) and add a probe failure injection point for testing. Also, update the logs for <g/h>uc_init failures to probe_failure() since they will cause the driver load to fail. Signed-off-by:
Fernando Pacheco <fernando.pacheco@intel.com> Reviewed-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by:
Andi Shyti <andi.shyti@intel.com> Signed-off-by:
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Daniele Ceraolo Spurio authored
To be able to differentiate the before and after of our commitment to GuC submission, which will be used in follow-up patches to early set-up the submission structures. v2: move functions to guc_submission.h (Michal) Signed-off-by:
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Daniele Ceraolo Spurio authored
To be able to setup GuC submission functions during engine init we need to commit to using GuC as soon as possible. Currently, the only thing that can stop us from using the microcontrollers once we've fetched the blobs is a fundamental error (e.g. OOM); given that if we hit such an error we can't really fall-back to anything, we can "officialize" the FW fetching completion as the moment at which we're committing to using GuC. To better differentiate this case, the uses_guc check, which indicates that GuC is supported and was selected in modparam, is renamed to wants_guc and a new uses_guc is introduced to represent the case were we're committed to using the GuC. Note that uses_guc does still not imply that the blob is actually loaded on the HW (is_running is the check for that). Also, since we need to have attempted the fetch for the result of uses_guc to be meaningful, we need to make sure we've moved away from INTEL_UC_FIRMWARE_SELECTED. All the GuC changes have been mirrored on the HuC for coherency. v2: split fetch return changes and new macros to their own patches, support HuC only if GuC is wanted, improve "used" state description (Michal) v3: s/wants_huc/uses_huc in uc_init_wopcm Signed-off-by: -
Daniele Ceraolo Spurio authored
We want to map uC-level checks to GuC/HuC-level ones. The mapping from the uC state to the GuC/HuC one follows the same pattern for all the functions: uc_xxx_guc() -> guc_is_yyy() So we can easily use a macro to autogenerate the functions via macros by passing in the 2 mapped states. v2: Split this change to its own patch (Michal) Signed-off-by:
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Daniele Ceraolo Spurio authored
In a follow up patch we will rely on the fact that the status always moves away from "SELECTED" after the fetch is attempted to decide what to do with the GuC. v2: Split this change to its own patch (Michal) Signed-off-by:
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Daniele Ceraolo Spurio authored
use intel_uc_uses_guc_submission() directly instead, to be consistent in the way we check what we want to do with the GuC. v2: do not go through ctx->vm->gt, use i915->gt instead Signed-off-by:
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Daniele Ceraolo Spurio authored
use intel_uc_uses_guc() directly instead, to be consistent in the way we check what we want to do with the GuC. v2: split guc_log_info changes to their own patch (Michal) Signed-off-by:
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Daniele Ceraolo Spurio authored
The log struct is the only thing the function needs (apart from the seq_file), so we can pass just that instead of the whole dev_priv. v2: Split this change to its own patch (Michal) Signed-off-by:
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Chris Wilson authored
In preparation for making GEM execbuf parallel, we need to be prepared to handle very early declaration of dependencies -- even before our signaler has itself been submitted. References: a79ca656 ("drm/i915: Push the wakeref->count deferral to the backend") Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200220123608.1666271-1-chris@chris-wilson.co.uk
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Chris Wilson authored
While we know that the waiters cannot disappear as we walk our list (only that they might be added), the same cannot be said for our signalers as they may be completed by the HW and retired as we process this request. Ergo we need to use rcu to protect the list iteration and remember to mark up the list_del_rcu. v2: Mark the deps as safe-for-rcu Fixes: 793c2261 ("drm/i915/gt: Protect execlists_hold/unhold from new waiters") Fixes: 32ff621f ("drm/i915/gt: Allow temporary suspension of inflight requests") Signed-off-by:
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Matthew Auld authored
The real one can be found in i915_scheduler.c. Signed-off-by:
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Manasi Navare authored
If one of the synced crtcs needs a full modeset, we need to make sure all the synced crtcs are forced a full modeset. v3: * Remove ~BIT(cpu_trans) which is a nop (Ville) * use get_new_crtc_state and remove error check (Ville) v2: * Add tiles based on cpu_trans check (Ville) Suggested-by:
Manasi Navare <manasi.d.navare@intel.com> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200214114126.13192-3-manasi.d.navare@intel.com
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Manasi Navare authored
This patch pushes out the computation of master and slave transcoders in crtc states after encoder's compute_config hook. This ensures that the assigned master slave crtcs have exact same mode and timings which is a requirement for Port sync mode to be enabled. v3: * Make crtc_state const, remove crtc state NULL init (Ville) v2: * Correct indentation * Rename to intel_ddi_port_sync_transcoders (Ville) * remove unwanted debug (Ville) Suggested-by:
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Ville Syrjälä authored
Add an optional secondary encoder state compute hook. This gets called after the normak .compute_config() has been called for all the encoders in the state. Thus in the new hook we can rely on all derived state populated by .compute_config() to be already set up. Should be useful for MST and port sync master/slave transcoder selection. Signed-off-by:
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- 19 Feb, 2020 8 commits
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Chris Wilson authored
For dgfx, we do not need to reconfigure the IA/ring frequencies of the main processors as they are distinct devices. Signed-off-by:
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Chris Wilson authored
Currently, we check that a new context has a clear set of general purpose registers. Add a little bit of hostility by preempting our new context and re-poisoning the GPR to ensure that there is no context leakage from preemption. Signed-off-by:
Ramalingam C <ramalingam.c@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200219123418.1447428-1-chris@chris-wilson.co.uk
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Chris Wilson authored
Check that the CTX_TIMESTAMP is monotonic across context save/restore and upon preemption. References: https://gitlab.freedesktop.org/drm/intel/issues/1233Signed-off-by:
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Chris Wilson authored
Read the rawclk_freq during runtime info probing, prior to its first use in computing the CS timestamp frequency. Then store it in the runtime info, and include it in the debug printouts. Closes: https://gitlab.freedesktop.org/drm/intel/issues/834Signed-off-by:
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Chris Wilson authored
On dgfx, we only use l3cc and not mocs, but we share the table containing both register definitions with Tigerlake. This confuses our selftest that verifies that both sets of registers do contain the values in our tables after various events (idling, reset, activity etc). When constructing the table of register definitions, also include the flags for which registers are valid so that information is computed centrally and available to all callers. Signed-off-by:
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Jani Nikula authored
Push irq uninstall further up, by splitting i915_driver_modeset_remove() to two, the part with working irqs before irq uninstall, and the part after irq uninstall. No functional changes. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Split intel_modeset_driver_remove() to two, the part with working irqs before irq uninstall, and the part after irq uninstall. Move irq_unintall() closer to the layer it belongs. The error path in i915_driver_modeset_probe() looks obviously weird after this, but remains as good or broken as it ever was. No functional changes. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
spinlock_t is one case where the typedef is to be preferred over struct spinlock. Fixes: 42fb60de ("drm/i915/gem: Don't leak non-persistent requests on changing engines") Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
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- 18 Feb, 2020 7 commits
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Chris Wilson authored
As we have the total runtime known to us, show it when dumping the engine state for debug. Signed-off-by:
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Chris Wilson authored
Always flush the tasklet if we have pending submissions in wait_for_submit(), so that even if we see the HW has started before we process its ack, when we return the execlists state is well defined. Fixes: 06289949 ("drm/i915/selftests: Check for any sign of request starting in wait_for_submit()") Signed-off-by:
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Chris Wilson authored
Just missed setting err along an interruptible error path for the intel_engine_pulse(). Signed-off-by:
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Chris Wilson authored
We only want to wait until the request has been submitted at least once; that is it is either in flight, or has been. References: fcf7df7a ("drm/i915/selftests: Check for the error interrupt before we wait!") Signed-off-by:
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Rafael Antognolli authored
It's not clear whether this workaround is final yet, but the BSpec indicates that userspace needs to set bit 9 of this register on demand: "To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA" Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2501Signed-off-by:
Rafael Antognolli <rafael.antognolli@intel.com> [mattrope: Tweaked comment while applying] Signed-off-by:
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Jani Nikula authored
The implicit "dev_priv" local variable use has been a long-standing pain point in the register access macros I915_READ(), I915_WRITE(), POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW(). Replace them with the corresponding new display engine register accessors intel_de_read(), intel_de_write(), intel_de_posting_read(), intel_de_read_fw(), and intel_de_write_fw(). No functional changes. Generated using the following semantic patch: @@ expression REG, OFFSET; @@ - I915_READ(REG) + intel_de_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - POSTING_READ(REG) + intel_de_posting_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE(REG, OFFSET) + intel_de_write(dev_priv, REG, OFFSET) @@ expression REG; @@ - I915_READ_FW(REG) + intel_de_read_fw(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE_FW(REG, OFFSET) + intel_de_write_fw(dev_priv, REG, OFFSET) Reviewed-by:
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Jani Nikula authored
The implicit "dev_priv" local variable use has been a long-standing pain point in the register access macros I915_READ(), I915_WRITE(), POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW(). Replace them with the corresponding new display engine register accessors intel_de_read(), intel_de_write(), intel_de_posting_read(), intel_de_read_fw(), and intel_de_write_fw(). No functional changes. Generated using the following semantic patch: @@ expression REG, OFFSET; @@ - I915_READ(REG) + intel_de_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - POSTING_READ(REG) + intel_de_posting_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE(REG, OFFSET) + intel_de_write(dev_priv, REG, OFFSET) @@ expression REG; @@ - I915_READ_FW(REG) + intel_de_read_fw(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE_FW(REG, OFFSET) + intel_de_write_fw(dev_priv, REG, OFFSET) Reviewed-by:
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- 17 Feb, 2020 4 commits
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Chris Wilson authored
The ringbuffer's vma is expected to be in the GGTT and that is now being checked, so make sure the mocked ring declares it so. Signed-off-by:
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Chris Wilson authored
Without selftests enabled, I915_SELFTEST_ONLY becomes a dummy, generating a bare '0'. This causes the compiler to complain about a useless line, and while we could use I915_SELFTEST_DECLARE instead, it is a bit messier. Move the selftest-only code to a helper and make that conditional on having selftests enabled. Reported-by:
kbuild test robot <lkp@intel.com> Signed-off-by:
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Jani Nikula authored
Prefer intel_uncore_* over I915_READ, I915_WRITE, and POSTING_READ. Reviewed-by:
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Jani Nikula authored
i915_drv.c is a fairly big file, and having very specific vlv/chv suspend/resume code in it is a distraction. Split it out to a new vlv_suspend.[ch] file. Reviewed-by:
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