- 19 Sep, 2022 40 commits
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Charlene Liu authored
[why] update hw dccg based on HW delta, and reuse common src code Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alvin Lee authored
[Why & How] If we find that DML requires pipe split, run through DML again because the DET allocation per pipe must be re-assigned. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Josip Pavic authored
[Why & How] Extend existing OTG state collection function to include the vertical interrupt 1 state. Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Josip Pavic <Josip.Pavic@amd.com> Tested-by:
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Robin Chen authored
[Why] The Sink device string ID1/ID2 use 5 bytes instead of 6 bytes, so the driver should compare the first 5 bytes only. Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Robin Chen <po-tchen@amd.com> Tested-by:
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muansari authored
[WHY] The Vstartup position should be as late as possible to maximize power saving with the current. Calculation of Vstartup in DML does not take into account as SDP signal. [HOW] Made necessary changes to calculate the correct Vstartup position in DML to account for AS SDP * Overriding the VBlankNom value in certain cases otherwise it will use the default value * Bypassing the condition for adjust_sync_Vstartup * Overriding vblank_nom_input with VBlankNom that is set in the SW Layer Reviewed-by:
muansari <muansari@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] This shouldn't trigger during tiled display hotplug/unplug but it does because one of the tiles can end up with a NULL plane state. This also doesn't guard against the hang that it was originally trying to resolve, and can instead cause DIO corruption due to OTG sync being lost. [How] This was reverted at one point out of DCN31 so revert it here too. Reviewed-by:
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Daniel Miess authored
[Why] DP DSC compliance failing for dcn314 due to ICH_RESET_AT_END_OF_LINE shift and mask being missing [How] Add in shift and mask for ICH_RESET_AT_END_OF_LINE Reviewed-by:
Daniel Miess <Daniel.Miess@amd.com> Tested-by:
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Aurabindo Pillai authored
[Why and How] Enable committing subvp config through DMCUB for DCN32 Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Jaehyun Chung authored
[Why] v1_5 display object table has no way for connectors to indicate which slot they are a part of, resulting in additional empty slots to appear in EDID management UI. [How] Assume that all connectors belong to the same slot. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Jaehyun Chung <jaehyun.chung@amd.com> Tested-by:
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Josip Pavic authored
[Why & How] Increase width of some variables to avoid comparing integers of different widths Reviewed-by:
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Dmytro Laktyushkin authored
[Why & How] Update after new measurment came in Reviewed-by:
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Rodrigo Siqueira authored
[Why and How] We are hitting k1/k2 assert when we are using a virtual signal in the test; as a result, we are failing some automated tests with a false positive. This commit addresses this issue by ignoring the assert condition if we use SIGNAL_TYPE_VIRTUAL. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
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Alvin Lee authored
[Why & How] We should not allocate any DET for the phantom pipes. Reviewed-by:
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Cruise Hung authored
[Why] When USB4 DP link training failed and fell back to lower link rate, the time slot calculation uses the verified_link_cap. And the verified_link_cap was not updated to the new one. It caused the wrong VC payload time-slot was allocated. [How] Updated verified_link_cap with the new one from cur_link_settings after the LT completes successfully. Reviewed-by:
Cruise Hung <Cruise.Hung@amd.com> Tested-by:
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Meenakshikumar Somasundaram authored
[Why] During hot plug of specific 5K tiled display, sometimes both the tiles are not synchronized resulting in distortion. The reason is that otgs of both the tiles goes out of sync when otg workaround (dcnxxx_disable_otg_wa) is applied for bandwidth optimization. The otg workaround reenables otg but otg synchronization context is not reset and hence dc_trigger_sync() does not resynchronize otg again. [How] Implement reset_sync_context_for_pipe() to reset the otg synchronization context for the disabled pipe and its slave pipes when otg workaround is applied. Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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George Shen authored
[Why] Current DCN3.2 logic for finding the dummy P-state index uses the DCN3.0 DML validation function instead of DCN3.2 DML. This can result in either unexpected DML VBA values, or unexpected dummy P-state index to be used. [How] Update the dummy P-state logic to use DCN3.2 DML validation function. Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
George Shen <george.shen@amd.com> Tested-by:
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Charlene Liu authored
[why] Expose few dchubbun functions in dcn31 and dcn32 to leverage. Reviewed-by:
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Pavle Kotarac authored
[WHY] New dcn301 has 2 less phys Reviewed-by:
Pavle Kotarac <Pavle.Kotarac@amd.com> Tested-by:
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Pavle Kotarac authored
[WHY] Adding new asic id for dcn301 Reviewed-by:
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Sherry Wang authored
[Why] Hostvm should be enabled/disabled accordding to the status of riommu_active, but hostvm always be disabled on DCN31 which causes underflow [How] Set correct hostvm flag on DCN31 Reviewed-by:
Sherry Wang <Yao.Wang1@amd.com> Tested-by:
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George Shen authored
[Why] The urgent latency override is useful when debugging issues relating to underflow. Current overridden variable is not correct and has no effect on DCN3.2 and DCN3.21 DML calculations. [How] For DCN3.2 and DCN3.21, override the correct urgent latency variable when bounding box override is present. Reviewed-by:
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Alvin Lee authored
[Why & How] Uncomment SubVP pipe split assignment in driver since FW headers are now promoted Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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zhikzhai authored
[why] We have minimal pipe split transition method to avoid pipe allocation outage.However, this method will invoke audio setup which cause audio output stuck once pipe reallocate. [how] skip audio setup for pipelines which audio stream has been enabled Reviewed-by:
zhikzhai <zhikai.zhai@amd.com> Tested-by:
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Hugo Hu authored
[Why] The desktop plane and full-screen game plane may have different gamut remap coefficients, if switching between desktop and full-screen game without updating the gamut remap will cause incorrect color. [How] Update gamut remap if planes change. Reviewed-by:
Hugo Hu <hugo.hu@amd.com> Tested-by:
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Ian Chen authored
[Why & How] Move extra panel power sequencer settings into panel_cofig struct. Reviewed-by:
Ian Chen <ian.chen@amd.com> Tested-by:
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Aric Cyr authored
This version brings along following fixes: - Port DCN30 420 logic to DCN32 - Remove some unused definitions from DCN32/321 - Remove dp dig pixle rate div policy from dcn314 - Fix dcn315 reading of memory channel count and width - Fix SubVP and ODM relevant issues - Fix pipe split, MPO and ODM relevant issues - Support proper mst payload removal when link is not in mst mode in dc - Assume an LTTPR is always present on fixed_vs links - Rework recent update PHY state commit - Add debug option and logs Acked-by:
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Anthony Koo authored
- Handle pipe split case for SubVP: Pass in pipe split index for main and phantom pipes Reviewed-by:
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Alvin Lee authored
[Why and How] - Don't skip bottom and next odm pipe when calculating num ways for subvp - Don't need to double cache lines for DCC (divide by 256) Reviewed-by:
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Alvin Lee authored
[Why and How] - For driver disable cases in current implementation, if P-State is unsupported or still supported by firmware, we force it supported by DCN. - SubVP now needs to be included in this case along with FPO. Reviewed-by:
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Alvin Lee authored
[Why and How] For SubVP pipe split case, pass in split index for main and phantom pipes to ensure that the P-State sequence will force P-State for all required pipes. Reviewed-by:
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Alvin Lee authored
[Why and How] - Add a debug option for allocating extra way for cursor - Remove usage of cache_cursor_addr since it's not gaurenteed to be populated - Include cursor size in MALL calculation if it exceeds the DCN cursor buffer size (and don't need extra way for cursor) Reviewed-by:
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Alvin Lee authored
[Why & How] ODM seamless transitions require DIV_MODE_AUTO. However, DIV_MODE_AUTO only works when all the horizontal timing params are divisible by the ODM combine factor. Therefore, disable the ODM 2:1 policy when the horizontal timing params are not divisible by 2. Reviewed-by:
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Wenjing Liu authored
[why] When user unplugs mst hubs, the current code will forcefully zero entire mst payload allocation table structure stored in link before we deallocate actual payload when disabling stream. During the first disable stream sequence, we will use current mst payload allocation table to determine if link should be turned off. Because we zero out it before we are disabling stream, the payload allocation table stored in link doesn't represent the actual allocation status, so we turn off link at the first disable stream without waiting until all streams' payloads have been deallocated. This avoilates the designed deallocation sequence and caused system hang in DP2 scenario. [how] Remove payload during deallocation and never zero payload allocation structure without actually deallocating payload. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Wenjing Liu authored
[why] Original change 594b237b ("drm/amd/display: Add interface to track PHY state") was implemented by assuming stream's dpms off is equivalent to PHY power off. This assumption doesn't hold in following situations: 1. MST multiple stream scenario, where multiple streams are sharing the same PHY output. Toggle dpms off for one of the stream doesn't power off the PHY due to the presence of other streams. 2. enable stream failure scenario, where enable stream fails due to failure of link training. This will cause DPMS off is set to false, while the actual PHY power state is off in certain cases. Due to the problematic assumption, the logic will skip disabling other streams for MST multiple stream scenario, therefore PHY is not actually powered off. [how] 1. Rework this refactor by moving PHY state update down to hardware level, where we update PHY state in place when hardware sequencer is actually changing the power state of the PHY hardware. 2. Reimplement symclk on TX off workaround in place when we are actually calling transmitter control to power off PHY in dcn32. Note the workaround is added due to the lack of proper software interface to set TX while keeping symclk on. We plan to address this interface problem so we can set TX off only without affecting symclk in future dcn versions. Fixes: 594b237b ("drm/amd/display: Add interface to track PHY state") Reviewed-by:
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Yifan Zhang authored
This patch addes MES and MES-KIQ version in debugfs. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Tim Huang <Tim.Huang@amd.com> Acked-by:
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Michael Strauss authored
[WHY] LTTPRs can in very rare instsances fail to increment DPCD LTTPR count. This results in aux-i LTTPR requests to be sent to the wrong DPCD address, which causes link training failure. [HOW] Override internal repeater count if fixed_vs flag is set for a given link Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Dmytro Laktyushkin authored
[Why & How] Correctly set ddr5 channel width to 8 bytes Reviewed-by:
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Leo Li authored
[Why] DC makes use of layer_index (zpos) when picking the HW plane to enable HW cursor on. However, some compositors will not attach zpos information to each DRM plane. Consequently, in amdgpu, we default layer_index to 0 and do not update it. This causes said DC logic to enable HW cursor on all planes of the same layer_index, which manifests as a double cursor issue if one of the planes is scaled (and hence scaling the cursor as well). [How] Use DRM core helpers to calculate a normalized_zpos value for each drm_plane_state under each crtc, within the atomic state. This helper will first consider existing zpos values, and if identical/unset, fallback to plane ID ordering. The normalized_zpos is then passed to dc_plane_info during atomic check for later use by the cursor logic. Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Tested-by:
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Alvin Lee authored
[Why and How] - Only consider pixel rate div policy for DCN32+ Reviewed-by:
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Leo Chen authored
[Why & How] Added logs for panel delays, spread_spectrum_percentage, and gpuclk_ss_percentage to facilitate debugging. Reviewed-by:
Leo Chen <sancchen@amd.com> Tested-by:
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