- 21 Aug, 2019 8 commits
-
-
Maxime Ripard authored
The sun4i_i2s_hw_params function already has a variable holding the value returned by params_width, so let's just use that variable instead of calling params_width multiple times. Signed-off-by:
Maxime Ripard <maxime.ripard@bootlin.com> Link: https://lore.kernel.org/r/f85a1c1e014080a4bbc3abd19bc8fdcb86f0981a.1566392800.git-series.maxime.ripard@bootlin.comSigned-off-by:
Mark Brown <broonie@kernel.org>
-
Maxime Ripard authored
The LRCK period field in the FMT0 register holds the number of LRCK period for one channel in I2S mode. This has been hardcoded to 32, while it really should be the physical width of the format, which creates an improper clock when using a 16bit format, with the i2s controller as LRCK master. Fixes: 7d299381 ("ASoC: sun4i-i2s: Add support for H3") Signed-off-by:
-
Maxime Ripard authored
The clock dividers function has been using the word size to compute the clock rate at which it's supposed to be running, but the proper formula would be to use the physical width and / or slot width in TDM. It doesn't make any difference at the moment since all the formats supported have the same sample width and physical width, but it's not going to last forever. Fixes: 7d299381 ("ASoC: sun4i-i2s: Add support for H3") Signed-off-by:
-
Maxime Ripard authored
The i2s controller supports TDM, for up to 8 slots. Let's support the TDM API. Signed-off-by:
-
Kuninori Morimoto authored
snd_soc_remove_dai_link() has card connected dai_link check. but 1) we need to call list_del() anyway, because it is "remove" function, 2) It is doing many thing for this card / dai_link already before checking dai_link. This patch removes poinless dai_link check Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by:
Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Link: https://lore.kernel.org/r/875zms1ldm.wl-kuninori.morimoto.gx@renesas.comSigned-off-by:
-
Kuninori Morimoto authored
snd_soc_initialize_card_lists() is doing card related INIT_LIST_HEAD(), but, it is already doing at snd_soc_register_card(). We don't need to do it separately. This patch merges these. Signed-off-by:
-
Daniel Baluta authored
Register map for i.MX8QM is similar with i.MX6 series. Integration of SAI IP into i.MX8QM SOC features a FIFO size of 64 X 32 bits samples. Signed-off-by:
Daniel Baluta <daniel.baluta@nxp.com> Link: https://lore.kernel.org/r/20190814082911.665-3-daniel.baluta@nxp.comSigned-off-by:
-
Daniel Baluta authored
SAI module on imx8qm features a register map similar with imx6 series (it doesn't have VERID and PARAM registers at the beginning of address spece). Also, it has one FIFO which can help up to 64 * 32 bit samples. Signed-off-by:
-
- 20 Aug, 2019 27 commits
-
-
Codrin Ciubotariu authored
This controller supports capture and playback running at the same time, with the limitation that both capture and playback must be configured the same way (sample rate, sample format, number of channels, etc). For this, we have to assure that the configuration registers look the same when capture and playback are initiated. This patch fixes a bug in which the controller is in master mode and the hw_params() callback fails for the second audio stream. The fail occurs because the divisors are calculated after comparing the configuration registers for capture and playback. The fix consists in calculating the divisors before comparing the configuration registers. BCLK and LRC are then configured and started only if the controller is not already running. Fixes: 7e0cdf545a55 ("ASoC: mchp-i2s-mcc: add driver for I2SC Multi-Channel Controller") Signed-off-by:Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Link: https://lore.kernel.org/r/20190820162411.24836-4-codrin.ciubotariu@microchip.comSigned-off-by:
-
Maxime Ripard authored
We've been limited to 2 channels in the driver while the controller supports from 1 to 8 channels, in both capture and playback. let's remove the hardcoded checks and numbers, and extend the range of channel numbers we can use. Signed-off-by:
-
Maxime Ripard authored
The channels number have been hardcoded to 2 so far, while the controller supports more than that. Remove the instance where it has been hardcoded to compute the BCLK divider, and pass it through as an argument to ease further support of more channels. Signed-off-by:
-
Maxime Ripard authored
The A83t and H3 have the same quirks, so it doesn't make sense to duplicate the quirks structure. Signed-off-by:
-
Maxime Ripard authored
Unlike the previous SoCs, the A83t, like the newer ones, need the LRCK bitfield to be set. Let's add it. Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Signed-off-by:
-
Maxime Ripard authored
The A83t, unlike previous SoCs, has the MCLK enable bit at the 8th bit of the CLK_DIV register, unlike what is declared in the driver. Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Signed-off-by:
-
Maxime Ripard authored
The A83t has the same bit fields offsets than the A10 and A31, while this was the first device with the new layout, fix that. Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Signed-off-by:
-
Maxime Ripard authored
The LRCK polarity "normal" polarity in the I2S/TDM specs and in the Allwinner datasheet are not the same. In the case where the i2s controller is being used as the LRCK master, it's pretty clear when looked at under a scope. Let's fix this, and add a comment to clear up as much the confusion as possible. Fixes: 7d299381 ("ASoC: sun4i-i2s: Add support for H3") Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Signed-off-by:
-
Maxime Ripard authored
The LRCK and BCLK polarity offsets on newer SoCs has been changed, yet the driver didn't take it into account for all of them. This was taken into account for the H3, but not the A83t. This was handled using a reg_field for the H3. However, the value in that field will not be the same, so reg_field is not adapted in that case. Let's change for proper calls with the regular values. Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Signed-off-by:
-
Maxime Ripard authored
The RX and TX counters registers offset have been swapped, fix that. Fixes: fa7c0d13 ("ASoC: sunxi: Add Allwinner A10 Digital Audio driver") Signed-off-by:
-
Maxime Ripard authored
From: Marcus Cooper <codekipper@gmail.com> The clock division dividers have changed between the older (A10/A31) and newer (H3, A64, etc) SoCs. While this was addressed through an offset on some SoCs, it was missing some dividers as well, so the support wasn't perfect. Let's introduce a pointer in the quirk structure for the divider calculation functions to use so we can have the proper range now. Signed-off-by:
Marcus Cooper <codekipper@gmail.com> [Maxime: Fix the commit log, use a field in the quirk structure] Signed-off-by:
-
Maxime Ripard authored
On the first generation of Allwinner SoCs (A10-A31), the i2s controller was using the MCLK as BCLK parent. However, this changed since the introduction of the A83t and BCLK now uses the module clock as its parent. Let's introduce a hook to get the parent rate and use that in our divider calculations. Fixes: 7d299381 ("ASoC: sun4i-i2s: Add support for H3") Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Signed-off-by:
-
Maxime Ripard authored
The two main generations of our I2S controller require a slightly different format configuration, mostly because of a quite different register layout and some additional registers being needed on the newer generation. This used to be controlled through a bunch of booleans, however this proved to be quite impractical, especially since a bunch of SoCs forgot to set those parameters and therefore were broken from that point of view. Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Signed-off-by:
-
Maxime Ripard authored
The two main generations of our I2S controller require a slightly different channel configuration, mostly because of a quite different register layout and some additional registers being needed on the newer generation. This used to be controlled through a bunch of booleans, however this proved to be quite impractical, especially since a bunch of SoCs forgot to set those parameters and therefore were broken from that point of view. Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Signed-off-by:
-
Mark Brown authored
-
Daniel Stuart authored
Every single baytrail chromebook sets PMC to 0, as can be seeing below by searching through coreboot source code: $ grep -rl "PMC_PLT_CLK\[0\]" . ./rambi/variants/glimmer/devicetree.cb ./rambi/variants/clapper/devicetree.cb ./rambi/variants/swanky/devicetree.cb ./rambi/variants/enguarde/devicetree.cb ./rambi/variants/winky/devicetree.cb ./rambi/variants/kip/devicetree.cb ./rambi/variants/squawks/devicetree.cb ./rambi/variants/orco/devicetree.cb ./rambi/variants/ninja/devicetree.cb ./rambi/variants/heli/devicetree.cb ./rambi/variants/sumo/devicetree.cb ./rambi/variants/banjo/devicetree.cb ./rambi/variants/candy/devicetree.cb ./rambi/variants/gnawty/devicetree.cb ./rambi/variants/rambi/devicetree.cb ./rambi/variants/quawks/devicetree.cb Plus, Cyan (only non-baytrail chromebook with max98090) also needs this patch for audio to work. Thus, this commit adds all the missing devices to bsw_max98090 quirk table, implemented by commit a182ecd3 ("ASoC: intel: cht_bsw_max98090_ti: Add quirk for boards using pmc_plt_clk_0"). Signed-off-by:
Daniel Stuart <daniel.stuart14@gmail.com> Link: https://lore.kernel.org/r/20190815171300.30126-1-daniel.stuart14@gmail.comSigned-off-by:
-
Maxime Ripard authored
The MCLK divider calculation is currently computing the ideal divider using the oversample rate, the sample rate and the parent rate. However, since we have access to the frequency is supposed to be running at already, and as it turns out we're using it to compute the oversample rate, we can just use the ratio between the parent rate and the MCLK rate to simplify a bit the formula. Signed-off-by:
-
Maxime Ripard authored
The sun4i_i2s_hw_params already has a variable holding the value returned by params_channels, so let's just use that variable instead of calling params_channels multiple times. Signed-off-by:
-
Maxime Ripard authored
The BCLK divider should be calculated using the parameters that actually make the BCLK rate: the number of channels, the sampling rate and the sample width. We've been using the oversample_rate previously because in the former SoCs, the BCLK's parent is MCLK, which in turn is being used to generate the oversample rate, so we end up with something like this: oversample = mclk_rate / sampling_rate bclk_div = oversample / word_size / channels So, bclk_div = mclk_rate / sampling_rate / word_size / channels. And this is actually better, since the oversampling ratio only plays a role because the MCLK is its parent, not because of what BCLK is supposed to be. Furthermore, that assumption of MCLK being the parent has been broken on newer SoCs, so let's use the proper formula, and have the parent rate as an argument. Fixes: 7d299381 ("ASoC: sun4i-i2s: Add support for H3") Fixes: 21faaea1 ("ASoC: sun4i-i2s: Add support for A83T") Fixes: 66ecce33 ("ASoC: sun4i-i2s: Add compatibility with A64 codec I2S") Signed-off-by:
-
Maxime Ripard authored
Since the introduction of the driver, a new managed helper for the dmaengine PCM registration has been created. Let's use it to simplify a bit our probe and remove functions. Signed-off-by:
-
Maxime Ripard authored
So far the regmap and the dmaengine PCM are registered after our component has been, which means that our driver isn't properly initialised by then. Let's fix that. Signed-off-by:
-
Michał Mirosław authored
Make '* Capture Mode' a mux. This makes DAPM know that in single-ended mode only inverting mux paths need to be enabled. Signed-off-by:
Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by:
Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/125cd3c9f298da9b08a4d6002d4c00d70a898950.1566298834.git.mirq-linux@rere.qmqm.plSigned-off-by:
-
Michał Mirosław authored
Trivial fix for typo in "Capture Inverting Mux"es' name. Signed-off-by:
-
Daniel Stuart authored
Every single baytrail chromebook sets PMC to 0, as can be seeing below by searching through coreboot source code: $ grep -rl "PMC_PLT_CLK\[0\]" . ./rambi/variants/glimmer/devicetree.cb ./rambi/variants/clapper/devicetree.cb ./rambi/variants/swanky/devicetree.cb ./rambi/variants/enguarde/devicetree.cb ./rambi/variants/winky/devicetree.cb ./rambi/variants/kip/devicetree.cb ./rambi/variants/squawks/devicetree.cb ./rambi/variants/orco/devicetree.cb ./rambi/variants/ninja/devicetree.cb ./rambi/variants/heli/devicetree.cb ./rambi/variants/sumo/devicetree.cb ./rambi/variants/banjo/devicetree.cb ./rambi/variants/candy/devicetree.cb ./rambi/variants/gnawty/devicetree.cb ./rambi/variants/rambi/devicetree.cb ./rambi/variants/quawks/devicetree.cb Plus, Cyan (only non-baytrail chromebook with max98090) also needs this patch for audio to work. Thus, this commit adds all the missing devices to bsw_max98090 quirk table, implemented by commit a182ecd3 ("ASoC: intel: cht_bsw_max98090_ti: Add quirk for boards using pmc_plt_clk_0"). Signed-off-by:
-
Jerome Brunet authored
The tohdmitx glue uses regmap MMIO so it should require it. Fixes: c8609f38 ("ASoC: meson: add g12a tohdmitx control") Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20190820123510.22491-1-jbrunet@baylibre.comSigned-off-by:
-
Jerome Brunet authored
Use the devm variant to get the formatter reset so it is properly freed on device removal Fixes: 751bd5db ("ASoC: meson: axg-tdm-formatter: add reset") Signed-off-by:
-
Kunihiko Hayashi authored
When transitioning to supend state, uniphier_aio_dai_suspend() is called and asserts reset lines and disables clocks. However, if there are two or more DAIs, uniphier_aio_dai_suspend() are called multiple times, and double reset assersion will cause. This patch defines the counter that has the number of DAIs at first, and whenever uniphier_aio_dai_suspend() are called, it decrements the counter. And only if the counter is zero, it asserts reset lines and disables clocks. In the same way, uniphier_aio_dai_resume() are called, it increments the counter after deasserting reset lines and enabling clocks. Fixes: 139a3420 ("ASoC: uniphier: add support for UniPhier AIO CPU DAI driver") Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1566281764-14059-1-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by:
-
- 16 Aug, 2019 5 commits
-
-
Pierre-Louis Bossart authored
Even if ALH has no specific configuration, we still need to handle the common parameters for all DAIs Signed-off-by:
Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20190815192018.30570-5-pierre-louis.bossart@linux.intel.comSigned-off-by:
-
Pierre-Louis Bossart authored
The Audio Link Hub DAI does not require any static configuration from topology for now. We still need to pass the frame rate and format to firmware. Signed-off-by:
-
Bard liao authored
Rename SOUNDWIRE to ALH. Signed-off-by:
Bard liao <yung-chuan.liao@linux.intel.com> Signed-off-by:
-
Daniel Baluta authored
Add dummy support for SAI/ESAI digital audio interface IPs found on i.MX8 boards. Signed-off-by:
-
Shengjiu Wang authored
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of modules during system suspend and resume procedure. Thus, AUDMUX needs to save all the values of registers before the system suspend and restore them after the system resume. Signed-off-by:
Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1565931794-7218-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by:
-
