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  1. 26 Sep, 2016 11 commits
  3. 12 Jul, 2016 1 commit
  5. 08 Jul, 2016 2 commits
  7. 13 May, 2016 1 commit
  9. 03 May, 2016 1 commit
  11. 06 Apr, 2016 1 commit
    • Kedareswara rao Appana's avatar
      dmaengine: vdma: Add 64 bit addressing support to the driver · b72db400
      Kedareswara rao Appana authored 
      
This VDMA  is a soft ip, which can be programmed to support
32 bit addressing or greater than 32 bit addressing.

When the VDMA ip is configured for 32 bit address space
the buffer address is specified by a single register
(0x5C for MM2S and 0xAC for S2MM channel).

When the  VDMA core is configured for an address space greater
than 32 then each buffer address is specified by a combination of
two registers.

The first register specifies the LSB 32 bits of address,
while the next register specifies the MSB 32 bits of address.

For example, 5Ch will specify the LSB 32 bits while 60h will
specify the MSB 32 bits of the first start address.
So we need to program two registers at a time.

This patch adds the 64 bit addressing support to the vdma driver.
Signed-off-by: default avatarAnurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: default avatarKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
      b72db400
  13. 11 Mar, 2016 1 commit
  15. 22 Feb, 2016 1 commit
  17. 21 Nov, 2015 1 commit
    • Arnd Bergmann's avatar
      ASoC: samsung: pass filter function as pointer · 9bdca822
      Arnd Bergmann authored 
      
As we are now passing the filter data as pointers to the drivers,
we can take the final step and also pass the filter function the
same way. I'm keeping this change separate, as there it's less
obvious that this is a net win.

Upsides of this are:

- The ASoC drivers are completely independent from the DMA engine
  implementation, which simplifies the Kconfig logic and in theory
  allows the same sound drivers to be built in a kernel that supports
  different kinds of dmaengine drivers.

- Consistency with other subsystems and drivers

On the other hand, we have a few downsides:

- The s3c24xx-dma driver now needs to be built-in for the ac97 platform
  device to be instantiated on s3c2440.

- samsung_dmaengine_pcm_config cannot be marked 'const' any more
  because the filter function pointer needs to be set at runtime.
  This is safe as long we don't have multiple different DMA engines
  in thet same system at runtime, but is nonetheless ugly.
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Reviewed-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      9bdca822
  19. 16 Nov, 2015 1 commit
  21. 27 Oct, 2015 1 commit
  23. 14 Oct, 2015 1 commit
  25. 24 Sep, 2015 1 commit
  27. 24 Aug, 2015 1 commit
  29. 23 Aug, 2015 1 commit
    • Lars-Peter Clausen's avatar
      dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller · 0e3b67b3
      Lars-Peter Clausen authored 
      
Add support for the Analog Devices AXI-DMAC DMA controller. This controller
is a soft peripheral that can be instantiated in a FPGA and is often used
in Analog Devices' reference designs for FPGA platforms.

The peripheral has various configuration options that can be selected at
synthesis time and influence the supported features of the instantiated
peripheral, those options are represented as device-tree properties to
allow the driver to behave accordingly.

The peripheral has a zero latency architecture, which means it is possible
to switch from one to the next descriptor without any delay. This is
archived by having a internal queue which can hold multiple descriptors.
The driver supports this, which means it will submit new descriptors
directly to the hardware until the queue is full and not wait for a
descriptor to complete before the next one is submitted. Interrupts are
used for the descriptor queue flow control.

Currently the driver supports SG, cyclic and interleaved slave DMA.
Signed-off-by: default avatarLars-Peter Clausen <lars@metafoo.de>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
      0e3b67b3
  31. 21 Aug, 2015 1 commit
    • Dave Jiang's avatar
      dmaengine: ioatdma: fix zero day warning on incompatible pointer type · aaecdebc
      Dave Jiang authored 
      
The 32bit build is creating this warning. Since we don't expect anyone
actually use this on 32bit, restrict ioatdma to be built only on x86_64.
This issue has long existed and only reason it's surfacing due to code
refactoring.

   drivers/dma/ioat/dma.c: In function 'ioat_timer_event':
>> drivers/dma/ioat/dma.c:870:39: warning: passing argument 2 of 'ioat_cleanup_preamble' from incompatible pointer type
     if (ioat_cleanup_preamble(ioat_chan, &phys_complete))
                                          ^
   drivers/dma/ioat/dma.c:577:13: note: expected 'u64 *' but argument is of type 'dma_addr_t *'
    static bool ioat_cleanup_preamble(struct ioatdma_chan *ioat_chan,
                ^
Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
      aaecdebc
  33. 20 Aug, 2015 1 commit
  35. 18 Aug, 2015 1 commit
  37. 28 Jul, 2015 1 commit
  39. 16 Jul, 2015 1 commit
  41. 26 May, 2015 1 commit
    • Robert Jarzmik's avatar
      dmaengine: pxa: add pxa dmaengine driver · a57e16cf
      Robert Jarzmik authored 
      This is a new driver for pxa SoCs, which is also compatible with the former
mmp_pdma.

The rationale behind a new driver (as opposed to incremental patching) was :

 - the new driver relies on virt-dma, which obsoletes all the internal
   structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the
   functions

 - mmp_pdma allocates dma coherent descriptors containing not only hardware
   descriptors but linked list information
   The new driver only puts the dma hardware descriptors (ie. 4 u32) into the
   dma pool allocated memory. This changes completely the way descriptors are
   handled

 - the architecture behind the interrupt/tasklet management was rewritten to be
   more conforming to virt-dma

 - the buffers alignment is handled differently
   The former driver assumed that the DMA channel stopped between each
   descriptor. The new one chains descriptors to let the channel running. This
   is a necessary guarantee for real-time high bandwid...
      a57e16cf
  43. 14 May, 2015 1 commit
  45. 27 Apr, 2015 1 commit
  47. 02 Apr, 2015 2 commits
  49. 01 Apr, 2015 1 commit
  51. 17 Mar, 2015 1 commit
  53. 07 Mar, 2015 1 commit
  55. 05 Feb, 2015 1 commit
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