- 18 Apr, 2023 40 commits
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Le Ma authored
To prepare for gc v9_4_3 specific feature. v2: fix exports (Alex) Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Le Ma authored
v1: Modify kiq_init/fini, mqd_sw_init/fini and enable/disable_kcq to adapt to multi-die case. Pass 0 as default to all asics with single xcc (Le) v2: squash commits to avoid breaking the build (Le) v3: unify naming style (Le) v4: apply the changes to gc v11_0 (Hawking) Signed-off-by:
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Le Ma authored
This will benifit the mqd indexing for kiq/kcq in multi XCD case. Signed-off-by:
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Le Ma authored
To allocate independent queue_bitmap for each XCD, then the old bitmap policy can be continued to use with a clear logic. Use mec_bitmap[0] as default for all non-GC 9.4.3 IPs. v2: squash commits to avoid breaking the build v3: unify naming style Signed-off-by:
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Le Ma authored
v1: more kiq instances are a available in SOC (Le) v2: squash commits to avoid breaking the build (Le) v3: make the conversion for gfx/mec v11_0 (Hawking) Signed-off-by:
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Nikita Zhandarovich authored
Several calls to ci_dpm_fini() will attempt to free resources that either have been freed before or haven't been allocated yet. This may lead to undefined or dangerous behaviour. For instance, if r600_parse_extended_power_table() fails, it might call r600_free_extended_power_table() as will ci_dpm_fini() later during error handling. Fix this by only freeing pointers to objects previously allocated. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: cc8dbbb4 ("drm/radeon: add dpm support for CI dGPUs (v2)") Co-developed-by:
Natalia Petrova <n.petrova@fintech.ru> Signed-off-by:
Nikita Zhandarovich <n.zhandarovich@fintech.ru> Signed-off-by:
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Tom Rix authored
cpp_check reports drivers/gpu/drm/amd/display/modules/freesync/freesync.c:1143:17: style: Variable 'oldest_index' is assigned a value that is never used. [unreadVariable] oldest_index = 0; ^ This variable is not used so remove. Signed-off-by:Tom Rix <trix@redhat.com> Signed-off-by:
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Alan Liu authored
[Why] After gpu-reset, sometimes the driver fails to enable vblank irq, causing flip_done timed out and the desktop freezed. During gpu-reset, we disable and enable vblank irq in dm_suspend() and dm_resume(). Later on in amdgpu_irq_gpu_reset_resume_helper(), we check irqs' refcount and decide to enable or disable the irqs again. However, we have 2 sets of API for controling vblank irq, one is dm_vblank_get/put() and another is amdgpu_irq_get/put(). Each API has its own refcount and flag to store the state of vblank irq, and they are not synchronized. In drm we use the first API to control vblank irq but in amdgpu_irq_gpu_reset_resume_helper() we use the second set of API. The failure happens when vblank irq was enabled by dm_vblank_get() before gpu-reset, we have vblank->enabled true. However, during gpu-reset, in amdgpu_irq_gpu_reset_resume_helper() vblank irq's state checked from amdgpu_irq_update() is DISABLED. So finally it disables vblank irq again. After gpu-reset, if there is a cursor plane commit, the driver will try to enable vblank irq by calling drm_vblank_enable(), but the vblank->enabled is still true, so it fails to turn on vblank irq and causes flip_done can't be completed in vblank irq handler and desktop become freezed. [How] Combining the 2 vblank control APIs by letting drm's API finally calls amdgpu_irq's API, so the irq's refcount and state of both APIs can be synchronized. Also add a check to prevent refcount from being less then 0 in amdgpu_irq_put(). v2: - Add warning in amdgpu_irq_enable() if the irq is already disabled. - Call dc_interrupt_set() in dm_set_vblank() to avoid refcount change if it is in gpu-reset. v3: - Improve commit message and code comments. Signed-off-by:
Alan Liu <HaoPing.Liu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Colin Ian King authored
There is a spelling mistake in the smu_i2c_bus_access prototype. Fix it. Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Signed-off-by:
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Bas Nieuwenhuizen authored
This info would be used by radv to figure out when we need to split a submission into multiple submissions. radv currently has a limit of 192 which seems to work for most gfx submissions, but is way too high for e.g. compute or sdma. Userspace is available at https://gitlab.freedesktop.org/bnieuwenhuizen/mesa/-/commits/ib-rejection-v3 v3: Completely rewrote based on suggestion of making it a separate query. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2498Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
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Bas Nieuwenhuizen authored
And ensure each ring supports that many submissions. This makes sure that we don't get surprises after the submission has been scheduled where the ring allocation actually gets rejected. My calculations on the existing limits: COMPUTE v10: 128 COMPUTE v11: 128 COMPUTE v6: 157 COMPUTE v7: 133 COMPUTE v8: 130 COMPUTE v9: 125 GFX v10: 208 GFX v11: 213 GFX v6: 154 (doubling this in the previous patch) GFX v7: 226 GFX v8: 213 GFX v9: 208 GFX v9 (SW): 208 SDMA CIK: 87 SDMA SI: 97 SDMA v2.4: 74 SDMA v3.0: 74 SDMA v4.0: 72 SDMA v5.0: 51 SDMA v6.0: 52 UVD ENC v6.0: 98 UVD ENC v7.0: 92 UVD v3.1: 124 UVD v4.2: 124 UVD v5.0: 83 UVD v6.0 (VM): 55 UVD v7.0: 51 VCE v2.0: 126 VCE v3.0 (VM): 98 VCE v4.0: 93 VCN DEC v1.0: 49 VCN DEC v2.0: 51 VCN DEC v3.0: 51 VCN ENC v1.0: 58 VCN ENC v2.0: 93 VCN ENC v3.0: 93 VCN ENC v4.0: 93 VCN JPEG v1.0: 17 VCN JPEG v2.0: 16 VCN JPEG v2.5: 17 VCN JPEG v3.0: 17 VCN JPEG v4.0: 17 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2498Reviewed-by:
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Bas Nieuwenhuizen authored
To ensure it supports 192 IBs per submission, so we can keep a simplified IB limit in the follow up patch without having to look at IP or GPU version. Reviewed-by:
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Alvin Lee authored
[Why&How] - Implement interface to program DTBCLK DTO’s according to reference DTBCLK returned by PMFW - This is required because DTO programming requires exact DTBCLK reference freq or it could result in underflow Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Arnd Bergmann authored
Three functions in the amdgpu display driver cause -Wmissing-prototype warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_resource.c:1858:6: error: no previous prototype for 'is_timing_changed' [-Werror=missing-prototypes] is_timing_changed() is actually meant to be a global symbol, but needs a proper name and prototype. Fixes: 17ce8a69 ("drm/amd/display: Add dsc pre-validation in atomic check") Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Wesley Chalmers authored
[WHY] Add log entry for when display refresh from MALL settings are sent to SMU. Fixes: 1664641e ("drm/amd/display: Add logger for SMU msg") Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Tianci Yin authored
[why] Since the variable fpu_recursion_depth is per-CPU type, it has one copy on each CPU, thread migration causes data consistency issue, then the call trace shows up. And preemption disabling can't prevent migration. [how] Disable migration to ensure consistency of fpu_recursion_depth. Reviewed-by:
Tianci Yin <tianci.yin@amd.com> Tested-by:
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Mikita Lipski authored
Extract edid's checksum and send it back for verification if EDID_TEST is requested. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Acked-by:
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Aurabindo Pillai authored
[Why&How] Remove incorrect early return in a device specific fifo reset workaround Reviewed-by:
Leo Li <sunpeng.li@amd.com> Reviewed-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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Hersen Wu authored
[Why&How] We were not returning -EINVAL on DSC atomic check fail. Add it. Fixes: 71be4b16 ("drm/amd/display: dsc validate fail not pass to atomic check") Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Tested-by:
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Eric Yang authored
[Why] If optimized init is done in FW. DCN init can be skipped in driver. This need to be communicated between driver and fw and maintain backwards compatibility. [How] Use DMUB scratch 0 bit 2 to indicate optimized init done in fw and use DMUB scatch 4 bit 0 to indicate drive supports the optimized flow so FW will perform it. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
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Dmytro Laktyushkin authored
[Why & How] Fix a typo for dcn315 line buffer bpp. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by:
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Daniel Miess authored
[Why] 1. It could hit bandwidth limitdation under single dimm memory when connecting 8K external monitor. 2. IsSupportedVidPn got validation failed with 2K240Hz eDP + 8K24Hz external monitor. 3. It's better to filter out such combination in EnumVidPnCofuncModality 4. For short term, filter out in dc bandwidth validation. [How] Force 2K@240Hz+8K@24Hz timing validation false in dc. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Daniel Miess <Daniel.Miess@amd.com> Tested-by:
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Jingwen Zhu authored
[Why] The eDP retrain will cause the DPCD 300 to be reset to default. And cause the brightness can't be set correctly. [How] delete the call to edp panel power control in both enable_link_output/disable_link_output entirely and only call edp panel control in enable_link_dp and disable_link_dp once. Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Jingwen Zhu <Jingwen.Zhu@amd.com> Tested-by:
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Michael Mityushkin authored
[Why] When link training during engine recovery, ASSR might fail causing panel mode to be reset to default. This should not happen for eDP as it will prevent the panel from turning back on. [How] Added dp_panel_mode to struct dc_link to remember previously applied panel mode. Do not reset panel mode to default while performing link training if previously used panel mode = eDP. Reviewed-by:
Michael Mityushkin <michael.mityushkin@amd.com> Tested-by:
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Dmytro Laktyushkin authored
[Why & How] Add options for dc odm debug. Reviewed-by:
Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Alex Hung authored
[Why & How] timing.dsc_cfg.num_slices_v can be zero and it is necessary to check before using it. This fixes the error "divide error: 0000 [#1] PREEMPT SMP NOPTI". Reviewed-by:
Alex Hung <alex.hung@amd.com> Tested-by:
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Anthony Koo authored
- Add DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command - Remove d3 entry event and instead check for stream mask - dmu: Enable timeout recovery and detection for p-state Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Alvin Lee authored
[Description] - Enable FPO + Vactive Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
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Alvin Lee authored
[Description] - Since we do not use optimized watermark settings for MALL, set D = A - PMFW uses Set D for d0i3.1, so driver should make D = A for the time being - If we choose to optimize in the future we can set watermarks D correctly Reviewed-by:
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Michael Mityushkin authored
[Why] Doing core_link_disable_stream or set_dpms_off when reinitializing hardware causes issue to repro with external display connected. This is unnecessary, blanking pixel data should be sufficient. [How] Call disable_pixel_data while reinitializing hardware instead of core_link_disable_stream or set_dpms_off. Reviewed-by:
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Nasir Osman authored
[why] When we force ODM combine with DSC, we lose several 8 bit and 10 bit modes in validation and thus not able to use HDR. This is due to the number of horizontal slices used in DSC not properly being accounted for currently when 2:1 ODM Combine is forced. [how] Enforce at least two horizontal slices are used for DSC when ODM combine is forced. Reviewed-by:
Nasir Osman <nasir.osman@amd.com> Tested-by:
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Iswara Nagulendran authored
[HOW&WHY] Write DPCD 721 bit 7 to high, and the appropriate luminance level to DPCD 734-736 if bit 4 from DPCD register 734 is high, indicating that the panel luminance control is enabled from the panel side. Reviewed-by:
Iswara Nagulendran <Iswara.Nagulendran@amd.com> Tested-by:
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Rodrigo Siqueira authored
To ensure that FAMS can be used, DC must check if there is VRR support. This commit adds the required configuration to ensure FAMS can be executed in the target system. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
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Hersen Wu authored
[Why] hdcp are enabled for asics from raven. for old asics which hdcp are not enabled, hdcp_workqueue are null. some access to hdcp work queue are not guarded with pointer check. [How] add hdcp_workqueue pointer check before access workqueue. Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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Josip Pavic authored
[Why & How] If dmub command queuing fails due to the inbox being full, flush the inbox and resubmit the comamnd. This was previously the default behavior but was lost in a refactor. Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Tested-by:
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Josip Pavic authored
[Why & How] Consolidate dmub access to a single interface. This makes it easier to add code in the future that needs to run every time a dmub command is requested (e.g. instrumentation, locking etc). Reviewed-by:
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Alvin Lee authored
[Description] - Having excessively large margin causes failure in the static schedulability check in some cases for SubVP + DRR - 100us of DRR margin is sufficient based on a weeks worth of stress testing on different display configs Reviewed-by:
Michael Strauss <Michael.Strauss@amd.com> Acked-by:
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Alvin Lee authored
[Description] - Previous bug fix for audio issue included dtbclk and p-state on the optimized boot path which is incorarect - We only care about DISPCLK in the optimized vs. non-optimized boot path to avoid audio issues Reviewed-by:
Saaem Rizvi <syedsaaem.rizvi@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Increse to 6 as that is the max surfaces supported asics can have. The is no practical use case yet, but this is valuable for pre-si validation. Reviewed-by:
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Hersen Wu authored
[Why] when amdgpu_dm_update_connector_after_detect is called two times successively with valid sink, memory allocated of aconnector->timing_requested for the first call is not free. this causes memeleak. [How] allocate memory only when aconnector->timing_requested is null. Reviewed-by:
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