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  1. 04 Jul, 2005 6 commits
    • David S. Miller's avatar
      [SPARC64]: Fix IRQ retry interval timer value on sparc64 PCI controllers. · 864ae180
      David S. Miller authored 
      Use '5' instead of 'infinity'.
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      864ae180
    • David S. Miller's avatar
      [SPARC64]: Small Schizo PCI controller programming tweaks. · 9fba62a5
      David S. Miller authored 
      Use macro instead of magic value for Tomatillo discard-
timeout interrupt enable register bit.

Leave OBP programming PTO value unless Tomatillo and
version >= 0x2.

If no-bus-parking property is present, explicitly clear
PCICTRL_PARK bit.
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      9fba62a5
    • David S. Miller's avatar
      [SPARC64]: Do proper DMA IRQ syncing on Tomatillo · bb6743f4
      David S. Miller authored 
      This was the main impetus behind adding the PCI IRQ shim.

In order to properly order DMA writes wrt. interrupts, you have to
write to a PCI controller register, then poll for that bit clearing.
There is one bit for each interrupt source, and setting this register
bit tells Tomatillo to drain all pending DMA from that device.

Furthermore, Tomatillo's with revision less than 4 require us to do a
block store due to some memory transaction ordering issues it has on
JBUS.
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      bb6743f4
    • David S. Miller's avatar
      [SPARC64]: Add support for IRQ pre-handlers. · 088dd1f8
      David S. Miller authored 
      This allows a PCI controller to shim into IRQ delivery
so that DMA queues can be drained, if necessary.

If some bus specific code needs to run before an IRQ
handler is invoked, the bus driver simply needs to setup
the function pointer in bucket->irq_info->pre_handler and
the two args bucket->irq_info->pre_handler_arg[12].

The Schizo PCI driver is converted over to use a pre-handler
for the DMA write-sync processing it needs when a device
is behind a PCI->PCI bus deeper than the top-level APB
bridges.

While we're here, clean up all of the action allocation
and handling.  Now, we allocate the irqaction as part of
the bucket->irq_info area.  There is an array of 4 irqaction
(for PCI irq sharing) and a bitmask saying which entries
are active.

The bucket->irq_info is allocated at build_irq() time, not
at request_irq() time.  This simplifies request_irq() and
free_irq() tremendously.

The SMP dynamic IRQ retargetting code got removed in this
change too.  It was disabled for a few months now, and we
can resurrect it in the future if we want.
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      088dd1f8
    • Christoph Hellwig's avatar
      [SPARC]: bpp: remove sleep_on usage · 06326e40
      Christoph Hellwig authored 
      Use schedule_timeout() instead of sleep_on + timer.  Totally untested
due to lack of hardware, but the changes are rather trivial.
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      06326e40
    • Raphael Assenat's avatar
      [SPARC64/COMPAT]: Add some compat ioctl for ppdev · e7270dec
      Raphael Assenat authored 
      The following patch adds some ioctls to include/linux/compat_ioctl.h
to allow using ppdev from the 32 bit user space on sparc64.

This patch also adds the PPDEV option in the sparc64 menu, near Parallel
printer support in the 'General machine setup' submenu.

All those ioctls seem to be compatible, since (correct me if I'm wrong)
they dont use the 'long' type. See include/linux/ppdev.h.

The application I used to test the new ioctls only used the following:
PPEXCL
PPCLAIM
PPNEGOT
PPGETMODES
PPRCONTROL
PPWCONTROL
PPDATADIR
PPWDATA
PPRDATA

But I beleive that the other ioctls will work fine.
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      e7270dec
  3. 03 Jul, 2005 21 commits
  5. 02 Jul, 2005 3 commits
  7. 01 Jul, 2005 10 commits
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