- 17 Feb, 2022 12 commits
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yipechai authored
Define amdgpu_ras_late_init to call all ras blocks' .ras_late_init. Signed-off-by:
yipechai <YiPeng.Chai@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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yipechai authored
1. Move calling ras block instance members from module internal function to the top calling xxx_ras_late_init. 2. Module internal function calls can only use parameter variables of xxx_ras_late_init instead of ras block instance members. Signed-off-by:
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yipechai authored
Remove redundant calls of ras_late_init in mca ras block. Signed-off-by:
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yipechai authored
Remove redundant calls of ras_late_init in mmhub ras block. Signed-off-by:
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yipechai authored
Remove redundant calls of ras_late_init in hdp ras block. Signed-off-by:
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yipechai authored
Modify .ras_late_init function pointer parameter so that it can remove redundant intermediate calls in some ras blocks. Signed-off-by:
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Prike Liang authored
Add 3.1.6 DCE IP and assign relevant sw DM function for the new DCE. Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Hansen Dsouza authored
Add core DC implementation for DCN316. Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Hansen Dsouza <Hansen.Dsouza@amd.com> Signed-off-by:
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Leo Li authored
Initialize DMUB for DCN316. Use same funcs as DCN31 for DCN316. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
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Prike Liang authored
- set DC version - add construct/destroy dc clock management function - register dcn interrupt handler Signed-off-by:
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Leo Li authored
Reviewed-by:
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Leo Li authored
Add register headers for the following IPs: - DCN 3.1.6 - DPCS 4.2.3 Acked-by:
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- 16 Feb, 2022 28 commits
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Prike Liang authored
Needed to properly initialize GC 10.3.7. Signed-off-by:
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Felix Kuehling authored
Reference: https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays CC: Changcheng Deng <deng.changcheng@zte.com.cn> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Prike Liang authored
Initialize SDMA engine firmware loading. Signed-off-by:
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Prike Liang authored
Set smu sw function and enable swSMU support for MP1. Signed-off-by:
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Prike Liang authored
Set psp sw funcs callback and firmware loading for MP0. Signed-off-by:
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Prike Liang authored
Set gfxhub function and configure VM for GC block. Signed-off-by:
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Sathishkumar S authored
update vcn and jpeg power gating flags for VCN 3.1.1 Signed-off-by:
Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Prike Liang authored
Add new revision ID for GC 10.3.7 and set cg/pg flags. Signed-off-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Prike Liang authored
Set nv_common_ip_block for GC 10.3.7. Signed-off-by:
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Prike Liang authored
Add SMUIO sw function for the new SMUIO block. Signed-off-by:
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Mario Limonciello authored
The message `Voltage value looks like a Leakage ID but it's not patched` shows up as an error on Dell Precision 3540. This doesn't cause functional problems and should be downgraded to info. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1162Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Prike Liang authored
add nbio sw func for the new 7.5.1 nbio block. Signed-off-by:
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Alex Deucher authored
Since this is an existing asic, adjust the code to follow the same logic as previously so the driver state is consistent. No functional change intended. Acked-by:
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Michel Dänzer authored
Even if PSR is allowed for a present GPU, there might be no eDP link which supports PSR. Fixes: 70897848 ("drm/amdgpu/display: Only set vblank_disable_immediate when PSR is not enabled") Reviewed-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
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Tao Zhou authored
Otherwise gpu reset will be triggered unconditionally in poison consumption. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Changcheng Deng authored
There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use "flexible array members" for these cases. The older style of one-element or zero-length arrays should no longer be used. Reference: https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arraysReported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Changcheng Deng <deng.changcheng@zte.com.cn> Acked-by:
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Roman Li authored
[Why] The previous change: "Add affected crtcs to atomic state for dsc mst unplug" forces modeset on all added crctc regardless whether timing changed or not. Per our implementation of dsc we need modeset only if timing changed. Otherwise dsc can be programmed incorrectly leading to dsc engine hang. [How] During atomic_check pre-compute dsc params. Only set mode_changed if timing is changed. Reviewed-by:
Hersen Wu <hersenwu@amd.com> Acked-by:
Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by:
Roman Li <Roman.Li@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Victor Skvortsov authored
if (!(tmp & flag)) condition will always evaluate to true when the flag is 0x0 (AMDGPU_RLCG_GC_WRITE). Instead check that address bits are cleared to determine whether the command is complete. Signed-off-by:
Victor Skvortsov <victor.skvortsov@amd.com> Tested-by:
Bokun Zhang <bokun.zhang@amd.com> Reviewed by: Shaoyun.liu <Shaoyun.liu@amd.com> Signed-off-by:
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Hersen Wu authored
[why] payload and slot number of display on dsc mst hub will be adjusted when there is change on any display on dsc hub. to monitor dsc enable/disable, pbn change, we need add log. [How] add mst_pbn to dc_dsc_config of dc_crtc_timing. add dsc, pbn, display name within dc_core_enable_stream, dc_core_disable_stream, dc_stream_log Reviewed-by:
Jerry Zuo <Jerry.Zuo@amd.com> Acked-by:
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Aric Cyr authored
This version brings along the following fixes: -Fixes bugs for dsc mst hub -Enables 29 denial itnerface by default -Fixes dmub outbox notificatoin Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Anthony Koo authored
Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Roman Li authored
[Why] When display topology changed on DSC hub we add all crtcs with dsc support to atomic state. Refer to patch:"drm/amd/display: Trigger modesets on MST DSC connectors" However the original implementation may skip crtc if the topology change caused by unplug. That potentially could lead to no-lightup or corruption on DSC hub after unplug event on one of the connectors. [How] Update add_affected_mst_dsc_crtcs() to use old connector state if new connector state has no crtc (undergoes modeset due to unplug) Fixes: 44be939f ("drm/amd/display: Trigger modesets on MST DSC connectors") Reviewed-by:
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Eric Yang authored
Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Eric Yang <Eric.Yang2@amd.com> Tested-by:
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Luben Tuikov authored
Add the "harvest" field to the IP attributes in the IP discovery sysfs visualization, as this field is present in the binary data. At the time of this commit, the harvest data isn't consistently correct in VBIOS, but it is exposed for completeness, in the hopes that VBIOS will be fixed in the future. Cc: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
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Charlene Liu authored
[why] display mapping change will involved pipe power gating on and off. when doing this too fase, sometimes usbc will have no display. check HW status, it is still in pipe power gating. [how] insert polling HW status to make sure the required state reached. also add dal registry key handling. Reviewed-by:
Sung joon Kim <Sungjoon.Kim@amd.com> Acked-by:
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Hersen Wu authored
[why] when unplug 1 dp from dsc mst hub, atomic_check new request dc_state only include info for the unplug dp. this will not trigger re-compute pbn for displays still connected to hub. [how] all displays connected to dsc hub are available in dc->current_state, by comparing dc->current_state and new request from atomic_chceck, it will provide info of displays connected to hub and do pbn re-compute. Reviewed-by:
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Meenakshikumar Somasundaram authored
[Why] Currently driver enables dmub outbox notification before oubox ISR is registered. During boot scenario, sometimes dmub issues hpd outbox message before driver registers ISR and those messages are missed. [How] Enable dmub outbox notification after outbox ISR is registered. Also, restructured outbox enable code to call from dm layer and renamed APIs. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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Evan Quan authored
Add a quirk in sienna_cichlid_ppt.c to fix some OEM SKU specific stability issues. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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