- 21 Jun, 2019 40 commits
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Jack Xiao authored
PSP leverages the existing fw loading function for vcn updating sram. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jack Xiao authored
Convert ucode id to the corresponding psp ucode id. Signed-off-by:
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Jack Xiao authored
Add VCN RAM ucode id in corresponding to psp ucode id. Signed-off-by:
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Jack Xiao authored
PSP supports to program vcn sram by ucode loading interface. Signed-off-by:
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Leo Liu authored
It will be the default for VCN2.x family Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Leo Liu authored
Pause the DPG when not doing decode Signed-off-by:
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Leo Liu authored
This is for using SRAM directly v2: rebase (Alex) Signed-off-by:
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Leo Liu authored
This will be the basic and used for DPG mode Signed-off-by:
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Leo Liu authored
Just for cleanup Signed-off-by:
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Kevin Wang authored
the od_settings is asic related data, so move it to asic file. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Kevin Wang authored
the set default od_setting is asic related function, so move thic code to vega20_ppt file. Signed-off-by:
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Kevin Wang authored
these callback functions is only used for vega20 asic, to be compatible other asics,need to move this code to vega20_ppt file Signed-off-by:
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Kevin Wang authored
use sw-smu clk type name to replace legacy clk type name Signed-off-by:
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Kevin Wang authored
the smu->mutex is internal lock resource in sw-smu, some functions will use it at the same time, so it maybe will cause deadlock issue. this patch fix this issue in smu_force_performance_level function. Signed-off-by:
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Jack Xiao authored
The dummy page for returning from PRT resides inside system memory, need set system flag bit in VM_L2_CNTL. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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tiancyin authored
add new registers: mmPA_SC_ENHANCE_1, mmTCP_CNTL, update registers: mmDB_DEBUG4, mmUTCL1_CTRL Reviewed-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by:
tiancyin <tianci.yin@amd.com> Signed-off-by:
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Alex Deucher authored
Signed-off-by: -
hersen wu authored
dc needs get uclk dpm table for bandwidth calculation Signed-off-by:
hersen wu <hersenxs.wu@amd.com> Acked-by:
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hersen wu authored
this is hw workaround to wake up azalia from d3. display asic and azalia are two different pci devices. while display asic wake from d3, current hw does not send signal to azalia. workaround: display driver ask smu send message to azalia device to let azalia wake up. Defintion of SMU message, like PPSMC_MSG_BacroAudioD3PME, is per asic. It is shared by different OS. Signed-off-by:
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hersen wu authored
when dc update clocks via smu, smu needs to know how many displays active. this interface is for dc notify number of active displays to smu. Signed-off-by:
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hersen wu authored
when dc set mode or color format in frame buffer change, it may request clock changes, like dispclk, dcfclk, uclk. after smu get clock requests, smu will make decision. Signed-off-by:
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Kevin Wang authored
remove smu callback: get_mclk, get_sclk. because the function smu_get_dpm_freq_range has the same function. Signed-off-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Kevin Wang authored
the smu mutex lock is unnecessary in smu hw init. Signed-off-by:
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Kevin Wang authored
add sw-CTF support for navi10 Signed-off-by:
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Hawking Zhang authored
Add missing return (rebase fix). Signed-off-by:
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Hawking Zhang authored
The thermal policy could be ASIC specific ones and depends on structures in pptable. As a result, get_thermal_temperature_range should be implemented as ppt funcs instead of smu funcs Signed-off-by:
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Kevin Wang authored
the fcuntion thermal_get_temperature will be access SmuMetrics_t data, the data structure is asic related, so move vega20_ppt to implement. Signed-off-by:
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Kevin Wang authored
the SmuMetrics_t table is asic related data structure. so move vega20_ppt file to implement. Signed-off-by:
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Kevin Wang authored
because this callback is not asic related function, so move it to top code level to support more asic (eg: navi10) Signed-off-by:
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Kevin Wang authored
enable uclk (mclk) dpm by default on navi10 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Kenneth Feng authored
enable ac/dc feature on navi10. currently we don't have the case to verify it. Signed-off-by:
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Kenneth Feng authored
on navi10, by default the below four features are enabled. gfxclk deep sleep: enabled and verified fw dstate: enabled and then soc ulv is verified dcefclk deep sleep: enabled and verified. notice that on different boards, due to the minimum dcefclk deep sleep setting in VBIOS, we may not see dcefclk deep sleep kicking in. Signed-off-by:
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Kevin Wang authored
miss sclk support in force_clk_levels function Signed-off-by:
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Tao Zhou authored
remove the divisor 4 Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Acked-by:
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Tao Zhou authored
disable DPM UCLK and SOC DS on A0 secure board Signed-off-by:
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Tao Zhou authored
To determine whether the board is secure or not. v2: rebase (Alex) Signed-off-by:
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Tao Zhou authored
Enable soc clk deep sleep. Signed-off-by:
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Kevin Wang authored
due to the smu dma/RTOS restriction, the interval of catching smu metric table should be more than 1ms. otherwise it will cause the gpu activity data corruption. Signed-off-by:
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Kevin Wang authored
this callback function is only call in read_sensor in smu_v11_0.c, so move this code to {asic}_ppt.c to implement as asic related function. Signed-off-by: -
Kevin Wang authored
this callback function is only call in read_sensor in smu_v11_0.c, so move this code to {asic}_ppt.c to implement as asic related function. Signed-off-by:
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