- 07 Aug, 2023 1 commit
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Francesco Dolcini authored
Add WM8904 based analog sound card to Dahlia carrier board. Signed-off-by:
Francesco Dolcini <francesco.dolcini@toradex.com> Tested-by:
Mark Brown <broonie@kernel.org> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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- 06 Aug, 2023 5 commits
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Fabio Estevam authored
Fix the regulator names as per rohm,bd71847-pmic.yaml to fix the following schema warnings: imx8mm-emcon-avari.dtb: pmic@4b: regulators:LDO1:regulator-name:0: 'LDO1' does not match '^ldo[1-6]$' Signed-off-by:
Fabio Estevam <festevam@denx.de> Signed-off-by:
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Fabio Estevam authored
Pass a single BD71847 clock entry to fix the following schema warning: imx8mm-var-som-symphony.dtb: pmic@4b: clocks: [[22], [0]] is too long from schema $id: http://devicetree.org/schemas/mfd/rohm,bd71847-pmic.yaml#Signed-off-by:
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Hui Wang authored
When we ran the stress-ng cache related stressors, we got the log as below: ubuntu@ubuntu:~$ stress-ng --l1cache 4 stress-ng: info: [656] defaulting to a 86400 second (1 day, 0.00 secs) run per stressor stress-ng: info: [656] dispatching hogs: 4 l1cache stress-ng: info: [657] stress-ng-l1cache: skipping stressor, cannot determine cache level 1 information from kernel This is because the l1 and l2 cache info is missing in the devicetree, ls1028a has dual cortex-a72 cores and has 48KB icache, 32KB dcache and 1MB l2 ucache: - icache is 3-way set associative - dcache is 2-way set associative - l2cache is 16-way set associative - line size are 64bytes Signed-off-by:
Hui Wang <hui.wang@canonical.com> Signed-off-by:
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Fabio Estevam authored
The 'fsl,spi-num-chipselects' property is not a valid one, so remove it. Signed-off-by:
Yannic Moog <y.moog@phytec.de> Signed-off-by:
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Fabio Estevam authored
The 'fsl,spi-num-chipselects' property is not a valid one, so remove it. Signed-off-by:
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- 30 Jul, 2023 27 commits
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Alexander Stein authored
Use id-gpios and vbus-gpios instead. Signed-off-by:
Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Alexander Stein authored
Fixes the warnings: at24 0-0053: supply vcc not found, using dummy regulator at24 0-0057: supply vcc not found, using dummy regulator Signed-off-by:
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Haibo Chen authored
Enable lpi2c7 bus, and enable i2c IO expander. Reviewed-by:
Clark Wang <xiaoning.wang@nxp.com> Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Signed-off-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
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Haibo Chen authored
Add 100MHz and 200MHz pinctrl setting for eMMC, and enable 8 bit bus mode to config the eMMC work at HS400ES mode. Also update to use Standard Drive Strength for USDHC pad to get a better signal quality per Hardware team suggests. Reviewed-by:
Sherry Sun <sherry.sun@nxp.com> Signed-off-by:
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Han Xu authored
Add spi-nor support. - 8 bit mode for RX/TX. - Set the clock rate to 200MHz. - add default/sleep pinctrl. Co-developed-by:
Han Xu <han.xu@nxp.com> Signed-off-by:
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Peng Fan authored
Enable CM33 node to support rpmsg feature. To use rpmsg, also need to enable mu node for mailbox doorbell and reserved memory node for vring, and data buffer. And reserved a piece DRAM memory for case that m33 images loaded in DRAM. Signed-off-by:
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Peng Fan authored
Add reserved memory node for CMA usage. Signed-off-by:
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Haibo Chen authored
Add flexspi node, flexspi has a special memory region mapped to 0x60000000~0x6fffffff. This region is for AHB usage. So add this region to SoC ranges. Signed-off-by:
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Peng Fan authored
Add cpuidle node and enable cpuidle for dual cores. The HW mode in Arm Trusted Firmware is SoC Application Power Domain Sleep mode. Signed-off-by:
Jacky Bai <ping.bai@nxp.com> Signed-off-by:
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Peng Fan authored
Add thermal node. Cooling map is not added, because frequency runtime changing not supported for now. Reviewed-by:
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Peng Fan authored
Set default clock rate and parents for SDHC[0,1,2]. The PLL3 PFD2 maximum frequency is 332Mhz, we can't set it to 389Mhz as USDHC clock parent. Because PLL3 PFD0 is used for NIC, PFD1 is used for audio, the only choice is PFD3 which can reach to 400Mhz. USDHC1 and USDHC2 maximum PCC clock rate is 200Mhz in Over Drive mode, and 100Mhz in Nominal/Low Drive mode, when PTE or PTF is used. The patch adjusts clock parent to PLL3 PFD3 DIV1 for USDHC0, PLL3 PFD3 DIV2 for USDHC1 and USDHC2. And set the max rate to meet restrictions. Signed-off-by:
Ye Li <ye.li@nxp.com> Signed-off-by:
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Peng Fan authored
Add i.MX8ULP CM33 node. Signed-off-by:
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Krzysztof Kozlowski authored
There is no "vselect-en" property, neither in the bindings nor in the Linux driver: imx8mm-phyboard-polis-rdk.dtb: pmic@8: regulators:ldo2: Unevaluated properties are not allowed ('vselect-en' was unexpected) Signed-off-by: -
Alexander Stein authored
Cadence USB3 bindings specify a specific reg order. Adjust DT entries to match the bindings. Signed-off-by:
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Alexander Stein authored
Alias names use dashes instead of underscores, fix this. Signed-off-by:
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Alexander Stein authored
Alias names use dashes instead of underscores, fix this. Silences also dtbs_check warning: imx8qxp-tqma8xqp-mba8xx.dtb: aliases: 'vpu_core0', 'vpu_core1', 'vpu_core2' do not match any of the regexes: '^[a-z][a-z0-9\\-]*$', 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/aliases.yaml#Signed-off-by:
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Tim Harvey authored
The Gateworks imx8mp-venice-gw73xx-2x consists of a SOM + baseboard. The GW702x SOM contains the following: - i.MX8M Plus SoC - LPDDR4 memory - eMMC Boot device - Gateworks System Controller (GSC) with integrated EEPROM, button controller, and ADC's - PMIC - SOM connector providing: - eQoS GbE MII - 1x SPI - 2x I2C - 4x UART - 2x USB 3.0 - 1x PCI - 1x SDIO (4-bit 3.3V) - 1x SDIO (4-bit 3.3V/1.8V) - GPIO The GW73xx Baseboard contains the following: - GPS - microSD - off-board I/O connector with SPI - off-board I/O connector with I2C, and GPIO - off-board I/O connector with MIPI DSI, MIPI CSI, I2C, and GPIO - off-board I/O connector with RS232 and RS485 - EERPOM - USB 3.0 HUB - USB 3.0 TypeA socket - USB 2.0 Micro-B OTG socket - Accelerometer - 1x GbE (eQoS) - 1x GbE (PCI) - PCIe clock generator - PCIe switch - 2x full-length miniPCIe socket with PCI and USB2.0 - 1x full-length miniPCIe socket with PCI/USB3 (via mux) SIM, and USB2.0 - 1x half-length miniPCIe socket with USB2.0 and USB3.0 - USB Type-C with USB PD Sink capability and peripheral support - USB Type-C with USB 3.0 host support - on-board 802.11abgnac with Bluetooth 5.2 - Wide range DC input supply Signed-off-by:
Tim Harvey <tharvey@gateworks.com> Signed-off-by:
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Tim Harvey authored
The Gateworks imx8mp-venice-gw72xx-2x consists of a SOM + baseboard. The GW702x SOM contains the following: - i.MX8M Plus SoC - LPDDR4 memory - eMMC Boot device - Gateworks System Controller (GSC) with integrated EEPROM, button controller, and ADC's - PMIC - SOM connector providing: - eQoS GbE MII - 1x SPI - 2x I2C - 4x UART - 2x USB 3.0 - 1x PCI - 1x SDIO (4-bit 3.3V) - 1x SDIO (4-bit 3.3V/1.8V) - GPIO The GW72xx Baseboard contains the following: - GPS - microSD - off-board I/O connector with SPI - off-board I/O connector with I2C, and GPIO - off-board I/O connector with MIPI DSI, MIPI CSI, I2C, and GPIO - off-board I/O connector with RS232 and RS485 - EERPOM - USB 3.0 HUB - USB 3.0 TypeA socket - USB 2.0 Micro-B OTG socket - Accelerometer - 1x GbE (eQoS) - 1x GbE (PCI) - PCIe clock generator - PCIe switch - 1x full-length miniPCIe socket with PCI and USB2.0 - 1x full-length miniPCIe socket with PCI/USB3 (via mux) SIM, and USB2.0 - 1x half-length miniPCIe socket with USB2.0 and USB3.0 - USB Type-C with USB PD Sink capability and peripheral support - USB Type-C with USB 3.0 host support - Wide range DC input supply Signed-off-by:
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Tim Harvey authored
The Gateworks imx8mp-venice-gw71xx-2x consists of a SOM + baseboard. The GW702x SOM contains the following: - i.MX8M Plus SoC - LPDDR4 memory - eMMC Boot device - Gateworks System Controller (GSC) with integrated EEPROM, button controller, and ADC's - PMIC - SOM connector providing: - eQoS GbE MII - 1x SPI - 2x I2C - 4x UART - 2x USB 3.0 - 1x PCI - 1x SDIO (4-bit 3.3V) - 1x SDIO (4-bit 3.3V/1.8V) - GPIO The GW71xx Baseboard contains the following: - GPS - RJ45 GbE (eQoS) - off-board I/O connector with UART, I2C, SPI, GPIO - EERPOM - PCIe clock generator - full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0 - USB Type-C with USB 2.0 host and peripheral support - Wide range DC input supply Signed-off-by:
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Tim Harvey authored
The Gateworks imx8mm-venice-gw7905-0x consists of a SOM + baseboard. The GW700x SOM contains the following: - i.MX8M Mini SoC - LPDDR4 memory - eMMC Boot device - Gateworks System Controller (GSC) with integrated EEPROM, button controller, and ADC's - PMIC - SOM connector providing: - FEC GbE MII - 1x SPI - 2x I2C - 4x UART - 2x USB 2.0 - 1x PCI - 1x SDIO (4-bit 3.3V) - 1x SDIO (4-bit 3.3V/1.8V) - GPIO The GW7905 Baseboard contains the following: - GPS - microSD - off-board I/O connector with I2C, SPI, GPIO - EERPOM - PCIe clock generator - 1x full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0 - 1x half-length miniPCIe socket with USB2.0 and USB3.0 - USB 3.0 HUB - USB Type-C with USB PD Sink capability and peripheral support - USB Type-C with USB 3.0 host support Signed-off-by:
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Tim Harvey authored
Add support for the following Raspberry Pi displays: - DFROBOT DRF0678 7in 800x480 TFT DSI capacitive touch - DFROBOT DRF0550 5in 800x480 TFT DSI capacitive touch Both have the following hardware: - FocalTech FT5406 10pt touch controller (with no interrupt) - Powertip PH800480T013-IDF02 compatible panel - Toshiba TC358762 compatible DSI to DBI bridge - ATTINY based regulator used for backlight controller and panel enable Support is added via a device-tree overlay. The touch controller is not yet supported as polling mode is needed. Signed-off-by:
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Hugo Villeneuve authored
USB OTG is currently not working for new versions of the Variscite Symphony EVK and imx8mn nano SOM (versions >= 1.4a). The PTN5150 circuitry on newer versions of the Symphony EVK board has a non-standard configuration in which the PTN5150 IRQ pin is left unconnected, and the PTN5150 ID pin is connected to GPIO1_IO11. This requires changes to the ptn5150 driver to support this new mode. Variscite have indicated their intention to submit those changes upstream. In the meantime, import device tree changes from linux-5.15 branch of varigit repos to at least make the USB OTG port operate correctly in host mode. Signed-off-by:
Hugo Villeneuve <hvilleneuve@dimonoff.com> Signed-off-by:
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Alexander Stein authored
Add coresight trace components (ETM, ETF, ETB and Funnel). ┌───────┐ ┌───────┐ ┌───────┐ │ CPU0 ├─►│ ETM0 ├─►│ │ └───────┘ └───────┘ │ │ │ │ ┌───────┐ ┌───────┐ │ ATP │ │ CPU1 ├─►│ ETM1 ├─►│ │ └───────┘ └───────┘ │ │ │ FUNNEL│ ┌───────┐ ┌───────┐ │ │ │ CPU2 ├─►│ ETM2 ├─►│ │ └───────┘ └───────┘ │ │ ┌─────┐ │ │ │ │ ┌───────┐ ┌───────┐ │ │ │ M4 │ │ CPU3 ├─►│ ETM3 ├─►│ │ │ │ └───────┘ └───────┘ └───┬───┘ └──┬──┘ AXI │ │ ▲ ▼ ▼ │ ┌───────────────────────────┐ ┌─────┐ ┌─┴──┐ │ ATP FUNNEL ├──►│ ETF ├─► │ETR │ └───────────────────────────┘ └─────┘ └────┘ Signed-off-by: -
Sebastian Krzyszkowiak authored
This appears to be enough for both Redpine and SparkLAN cards. Waiting for too long makes us waste time in resume from system suspend, so let's keep it as short as possible. Signed-off-by:
Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Signed-off-by:
Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by:
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Sebastian Krzyszkowiak authored
This allows to wake up from system suspend on USB-C plug/unplug. Signed-off-by:
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Sebastian Krzyszkowiak authored
There is at least one Evergreen phone out there that reports levels of 5-6 at rest: https://gitlab.gnome.org/GNOME/calls/-/issues/560Signed-off-by:
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Martin Kepplinger authored
Unfortunately the codec can't be switched off on it's own. It would ground the whole bus it's connected to (because of it's built-in diodes to VDD on i2c pins), making all the other devices on the same bus inaccessible: [ 0.237154] lm3692x 2-0036: Cannot read/clear faults: -11 [ 0.242628] lm3692x 2-0036: Fail writing initialization values [ 0.286462] [drm:drm_bridge_attach] *ERROR* failed to attach bridge /soc@0/bus@30800000/mipi-dsi@30a00000 to encoder None-34: -517 Work around this hardware limitation by keeping audio-1v8 enabled. Signed-off-by:
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- 19 Jul, 2023 7 commits
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Jonas Kuenstler authored
Add the missing usdhc2 root clock to 200MHz to be able to support SDR104 mode for SD-Card on phyBOARD-Pollux-i.MX8MP. Signed-off-by:
Jonas Kuenstler <j.kuenstler@phytec.de> Signed-off-by:
Teresa Remmet <t.remmet@phytec.de> Signed-off-by:
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Teresa Remmet authored
Set the regulator voltages to the min and max values the i.MX8MP requires and not what the PMIC provides. Signed-off-by:
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Teresa Remmet authored
Add regulator-names for more meaningful description. Signed-off-by:
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Teresa Remmet authored
We do not touch LDO2 and LDO4 in linux as they are bypassed. So remove them completely from device tree. Signed-off-by:
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Teresa Remmet authored
Do not set reserved bits 0 and 3 in pad configuration. Signed-off-by:
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Teresa Remmet authored
Rearrange properties in order: - compatible - reg - other generic properties - device specific properties - vendor specific properties - status And use alphabetical order inside a group. Signed-off-by:
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Christian Hemp authored
In some occasions the ethernet phy IRQ can not be detected correctly by the SoC. This leads to a non detected link in Linux. The problem is caused by the buffer that adjusts the voltage between ethernet phy and SoC. To workaround this, remove the IRQ support for the ethernet phy and use polling instead. Signed-off-by:
Christian Hemp <c.hemp@phytec.de> Signed-off-by:
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