- 09 Apr, 2024 1 commit
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Jani Nikula authored
The same info is available in i915_cdclk_info. Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by:
Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/50461f13ab09b162de25d3f3587890548f4db499.1712599670.git.jani.nikula@intel.com
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- 08 Apr, 2024 20 commits
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Ville Syrjälä authored
With bigjoiner the master crtc is the one that will send out the uapi event/etc. We want that to happen after all the slaves are done, so let's try to do the commits in reverse order so that the master comes last. Even worse, the modeset helper will simply complete the commit on the slave pipe immediately as it consider the crtc to be inactive (it can't see our crtc_state->hw.active/etc.). With regular sync updates this generally doesn't matter all that much as the slave pipe should typically finish its work during the same frame as the master pipe. However in case the slave pipe's commit slips into the next frame we end up in a bit of trouble. This is most visible with either async flips (currently disabled with bigjoiner exactly for this reason), and DSB gamma updates. With DSB the problem happens because the DSB itself will wait until the next start vblank before starting to execute. So if the master pipe already finished its commit and the DSB on the slave pipe is still waiting for the next vblank we will assume the DSB as gotten stuck and terminate it. Reversing the commit order should ameliarate this for the most part as the master pipe is guaranteed to start its commit after the slave pipe started. The one thing that can still screw us over is the fact that we aren't necessarily going to commit the pipes in the reverse order as the actual order is dictated by the DDB overlap avoidance. But that can only happen while other pipes are being enabled/disabled, and so in the normal steady state we should be safe. The full fix will involve making the commit machinery aware of the slave pipes and not finish their commits prematurely. But that will involve a bit more work than this. And this commit order reversal will still be beneficial to avoid userspace getting an -EBUSY from the following page flip if the second pipe's commit does stretch into the next frame. Signed-off-by:
Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by:
Vandita Kulkarni <vandita.kulkarni@intel.com>
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Ville Syrjälä authored
Currently intel_modeset_pipe_config_late() is called after the bigjoiner state copy, and it will actually not do anything for bigjoiner slaves. This can lead to a mismatched state between the master and slave. The two things that we do in the encoder .compute_config_late() hook are mst master transcoder and port sync master transcoder elections. So if either of either MST or port sync is combined with bigjoiner then we can see the mismatch. Currently this problem is more or less theoretical; MST+bigjoiner has not been implemented yet, and port sync+bigjoiner would require a tiled display with >5k tiles (or a very high dotclock per tile). Although we do have kms_tiled_display in igt which can fake a tiled display, and we can now force bigjoiner via debugfs, so it is possible to trigger this if you try hard enough. Reorder the code such that intel_modeset_pipe_config_late() will be called before the bigjoiner state copy happens so that both pipes will end up with the same state. Tested-by:
Vidya Srinivas <vidya.srinivas@intel.com> Reviewed-by:
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Ville Syrjälä authored
All joined pipes share the same transcoder/timing generator. Currently we just do the commits per-pipe, which doesn't really work if we need to change switch between non-VRR and VRR timings generators on the fly, or even when sending the push to the transcoder. For now just disable VRR when bigjoiner is needed. Cc: stable@vger.kernel.org Tested-by:
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Ville Syrjälä authored
All joined pipes share the same transcoder/timing generator. Currently we just do the commits per-pipe, which doesn't really work if we need to change the timings at the same time. For now just disable live M/N updates when bigjoiner is needed. Cc: stable@vger.kernel.org Tested-by:
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Ville Syrjälä authored
The current modeset sequence can't handle port sync and bigjoiner at the same time. Refuse port sync when bigjoiner is needed, at least until we fix the modeset sequence. v2: Add a FIXME (Vandite) Cc: stable@vger.kernel.org Tested-by:
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Ville Syrjälä authored
Bigjoiner seem to be causing all kinds of grief to the PSR code currently. I don't believe there is any hardware issue but the code simply not handling this correctly. For now just disable PSR when bigjoiner is needed. Cc: stable@vger.kernel.org Link: https://patchwork.freedesktop.org/patch/msgid/20240404213441.17637-3-ville.syrjala@linux.intel.comReviewed-by:
Arun R Murthy <arun.r.mruthy@intel.com> Acked-by:
Jouni Högander <jouni.hogander@intel.com> Signed-off-by:
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Jani Nikula authored
There's a bunch of unnecessary stuff not needed by display code. Remove. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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Jani Nikula authored
It's only there for GEM_BUG_ON(), but the display code no longer uses it. Good riddance. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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Jani Nikula authored
There's a bunch of unused cruft. Just throw away. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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Jani Nikula authored
All the users are in display, move the fixed point header under display. We could also consider making these more general purpose things, but that takes a bunch more effort. This allows the immediate cleanup of xe compat i915_fixed.h. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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Jani Nikula authored
Avoid the dependency on intel_uc_fw.h, and allow removal of xe compat intel_uc_fw.h. If there needs to be duplication of the URL, at least have the duplication in a sensible way. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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Jani Nikula authored
Avoid direct IS_PLATFORM() usage when we have the platform helpers. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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Jouni Högander authored
Panel replay has to be enabled on sink side before link training. Take this into account in fastset check and in initial fastset check. Signed-off-by:
Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-9-jouni.hogander@intel.com
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Jouni Högander authored
Unify enabling and disabling of psr/panel replay for a sink. Modify intel_psr_enable_sink accordingly and use it for both cases. v3: - move psr2_su_region_et_valid to be check for PSR2 only v2: - enable panel replay for sink before link training - write ALPM_CONFIG only for PSR - add DP_PSR_CRC_VERIFICATION only for PSR - take care of disable sink as well Signed-off-by:
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Jouni Högander authored
Bspec is saying this mask register: Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug] are used in panel replay mode. Status register: Only SRD_STATUS[SRD state] field is used in panel replay mode. Due to this stop writing and reading registers and bits not used by panel replay if panel replay is used. Bspec: 53370, 68920 v2: - use intel_dp_is_edp with PSR_MASK register - handle LunarLake as well - hanle ALPM configuration as well Signed-off-by:
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Jouni Högander authored
On HPD interrupt we want to check if the reason for HPD was some panel replay error detected by monitor/panel. This is already done for PSR. We want to do this for panel replay as well. Modify intel_psr_short_pulse to support panel replay as well. Signed-off-by:
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Jouni Högander authored
Currently panel replay is supporting only main link on mode -> Do not update phy power state for non-eDP panel replay. Bspec: 53370 v2: use intel_dp_is_edp to differentiate Signed-off-by:
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Jouni Högander authored
Currently intel_psr_pause and intel_psr_resume do nothing in case of panel replay. Change them to perform pause and return also in case of panel replay. Signed-off-by:
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Jouni Högander authored
Current code is setting only intel_crtc_state->has_panel_replay in panel replay case. There are lots of stuff behind intel_crtc_state->has_psr that is needed for panel replay as well. Instead of converting each check to has_psr || has_panel_replay set has_psr in case of panel replay as well. Code can then differentiate between psr and panel replay by using intel_crtc_state->has_panel_replay. Signed-off-by:
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Jouni Högander authored
We are adding more boolean variable into intel_psr and intel_crtc_state structs. Add some documentation about these for sake of clarity. v2: Modify has_psr + has_panel_replay to mean panel replay Signed-off-by:
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- 06 Apr, 2024 1 commit
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Ville Syrjälä authored
Currently intel_connector_info(), which prints the per-connector output for i915_display_info, just bails out early if the connector doesn't have a current encoder. That leads to very confusing output where some of your connected (and properly detected) outputs appear to have no enumerated modes. Get rid of the encoder stuff and just rely on the connector itself so that the output is always consistent. Signed-off-by:
Suraj Kandpal <suraj.kandpal@intel.com>
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- 05 Apr, 2024 2 commits
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Suraj Kandpal authored
HDCP 1.x capability needs to be checked even if setup is not HDCP 2.x capable. --v2 -Assign hdcp_capable and hdcp2_capable to false [Chaitanya] --v3 -Fix variable assignment [Chaitanya] Fixes: 813cca96 ("drm/i915/hdcp: Add new remote capability check shim function") Signed-off-by:
Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by:
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Suraj Kandpal authored
Initialize HDCP capability variables to false to avoid UBSAN warning in boolean value as some functions invoking this could return without filling the two capability values. --v2 -Fix Typo [Chaitanya] Signed-off-by:
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- 04 Apr, 2024 16 commits
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Ville Syrjälä authored
if the new dbuf slices are a superset of the old dbuf slices then we don't have to do anything in intel_dbuf_post_plane_update(). Restructure the code to skip such redundant dbuf slice updates. The main benefit is slightly less confusing logs. Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Signed-off-by:
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Ville Syrjälä authored
No point in throwing around u8 when we're dealing with just an integer. Use a plain old boring 'int'. Reviewed-by:
Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by:
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Stanislav Lisovskiy authored
Currently we can't change MBUS join status without doing a modeset, because we are lacking mechanism to synchronize those with vblank. However then this means that we can't do a fastset, if there is a need to change MBUS join state. Fix that by implementing such change. We already call correspondent check and update at pre_plane dbuf update, so the only thing left is to have a non-modeset version of that. If active pipes stay the same then fastset is possible and only MBUS join state/ddb allocation updates would be committed. The full mbus/cdclk sequence will look as follows: 1. disable pipes 2. increase cdclk if necessary 2.1 reprogram cdclk 2.2 update dbuf tracker value 3. enable mbus joining if necessary 3.1 update mbus_ctl 3.2 update dbuf tracker value 4. reallocate dbuf for planes on active pipes 5. disable mbus joining if necessary 5.1 update dbuf tracker value 5.2 update mbus_ctl 6. enable pipes 7. decrease cdclk if necessary 7.1 update dbuf tracker value 7.2 reprogram cdclk And in order to keep things in sync we need: Step 2: - mbus_join == old - mdclk/cdclk ratio == new Step 3: - mbus_join == new - mdclk/cdclk ratio == old when cdclk is changing in step 7 - mdclk/cdclk ratio == new when cdclk is changing in step 2 Step 5: - mbus_join == new - mdclk/cdclk ratio == old when cdclk is changing in step 7 - mdclk/cdclk ratio == new when cdclk is changing in step 2 Step 7: - mbus_join == new - mdclk/cdclk ratio == new v2: - Removed redundant parentheses(Ville Syrjälä) - Constified new_crtc_state in intel_mbus_joined_pipe(Ville Syrjälä) - Removed pipe_select variable(Ville Syrjälä) [v3: vsyrjala: Correctly sequence vs. cdclk updates, properly describe the full sequence, shuffle code around to make the diff more legible, streamline a few things] [v4: vsyrjala: Move the intel_cdclk_is_decreasing_later() stuff to a separate patch] Cc: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> #v3 Signed-off-by:Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Co-developed-by:
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Ville Syrjälä authored
The current cdclk/mbus programming sequence is as follows: 1. intel_set_cdclk_pre_plane_update() 2. update_mbus_pre_enable() 3. intel_set_cdclk_post_plane_update() when the actual mdclk/cdclk programming is postponed to intel_set_cdclk_post_plane_update() we must keep using the old mdclk/cdclk ratio during update_mbus_pre_enable(). This guarantees the programmed ratio matches the rest of the hardware state (mdlk/cdclk/mbus joining). v2: Extracted from the vblank synchronized mbus programming patch Cc: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> #v1 Signed-off-by:
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Stanislav Lisovskiy authored
In order to make sure we are not breaking the proper sequence let's do updates step by step and don't change MBUS join value during MDCLK/CDCLK programming stage. MBUS join programming would be taken care by pre/post ddb hooks. v2: - Reworded comment about using old mbus_join value in intel_set_cdclk(Ville Syrjälä) Reviewed-by: -
Ville Syrjälä authored
Add some debugs so that we can actually observe what is actually happening during the mbus/dbuf programming steps. We can just shove them into fairly low level functions as none of them are called during any critical sections/etc. Reviewed-by:
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Ville Syrjälä authored
Extract the stuff that writes the dbuf/mbus ratio stuff into its own function. Will help with correctly sequencing the operations done during mbus programming. Reviewed-by:
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Ville Syrjälä authored
Extact the stuff that writes the joining bits in MBUS_CTL into its own function. Will help with correctly sequencing the operations done during mbus programming. Reviewed-by:
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Ville Syrjälä authored
intel_mbus_dbox_update() will become static soon. Relocate it into a place that avoids having to add a forward declaration for it. Reviewed-by:
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Stanislav Lisovskiy authored
We need to loop through all active pipes, not just the ones, that are in current state, because disabling and enabling even a particular pipe affects credits in another one. Reviewed-by:
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Ville Syrjälä authored
Currently we just get a plain "Changing CDCLK to ..." in the logs. It would actually be interesting to see whether we're doing the programming during the pre or post plane phase of the commit. Include that information in the debug message. Reviewed-by:
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Ville Syrjälä authored
No one ever figured out why bumping the cdclk helped with whatever issue we were having at the time. Remove the hacks and start from scratch so that we can actually see if any problems still remain. Reviewed-by:
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Ville Syrjälä authored
Currently we only consider the relationship of the old and new CDCLK frequencies when determining whether to do the repgramming from intel_set_cdclk_pre_plane_update() or intel_set_cdclk_post_plane_update(). It is technically possible to have a situation where the CDCLK frequency is decreasing, but the voltage_level is increasing due a DDI port. In this case we should bump the voltage level already in intel_set_cdclk_pre_plane_update() (so that the voltage_level will have been increased by the time the port gets enabled), while leaving the CDCLK frequency unchanged (as active planes/etc. may still depend on it). We can then reduce the CDCLK frequency to its final value from intel_set_cdclk_post_plane_update(). In order to handle that correctly we shall construct a suitable amalgam of the old and new cdclk states in intel_set_cdclk_pre_plane_update(). And we can simply call intel_set_cdclk() unconditionally in both places as it will not do anything if nothing actually changes vs. the current hw state. v2: Handle cdclk_state->disable_pipes v3: Only synchronize the cd2x update against the pipe's vblank when the cdclk frequency is changing during the current commit phase (Gustavo) Cc: stable@vger.kernel.org Cc: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: -
Ville Syrjälä authored
Currently we always reprogram CDCLK from the intel_set_cdclk_pre_plane_update() when using squash/crawl. The code only works correctly for the cd2x update or full modeset cases, and it was simply never updated to deal with squash/crawl. If the CDCLK frequency is increasing we must reprogram it before we do anything else that might depend on the new higher frequency, and conversely we must not decrease the frequency until everything that might still depend on the old higher frequency has been dealt with. Since cdclk_state->pipe is only relevant when doing a cd2x update we can't use it to determine the correct sequence during squash/crawl. To that end introduce cdclk_state->disable_pipes which simply indicates that we must perform the update while the pipes are disable (ie. during intel_set_cdclk_pre_plane_update()). Otherwise we use the same old vs. new CDCLK frequency comparsiong as for cd2x updates. The only remaining problem case is when the voltage_level needs to increase due to a DDI port, but the CDCLK frequency is decreasing (and not all pipes are being disabled). The current approach will not bump the voltage level up until after the port has already been enabled, which is too late. But we'll take care of that case separately. v2: Don't break the "must disable pipes case" v3: Keep the on stack 'pipe' for future use Cc: stable@vger.kernel.org Fixes: d62686ba ("drm/i915/adl_p: CDCLK crawl support for ADL") Reviewed-by:
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Mitul Golani authored
Add read/write calls for Adaptive Sync SDP. Signed-off-by:
Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
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Mitul Golani authored
Compute vrr_vsync_start/end, which sets the position for hardware to send the Vsync at a fixed position relative to the end of the Vblank. --v2: - Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit) - Updated bit fields of VRR_VSYNC_START/END. (Ankit) --v3: - Add PIPE_CONF_CHECK_I(vrr.vsync_start/end). - Read/write vrr_vsync params only when we intend to send adaptive_sync sdp. --v4: - Use VRR_SYNC_START/END macros correctly. --v5: - Send AS SDP only when VRR is enabled. --v6: - Add TRANS_VRR_VSYNC before enabling VRR as per bspec. (Ankit) Signed-off-by:
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