- 15 May, 2018 40 commits
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Shirish S authored
FBC is not applicable for the underlay pipe, hence disallow enabling and disabling of the same. This also fixes the BUG hit of calling sleep in atomic context. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Michel Dänzer authored
Allocating up to 32 physically contiguous pages can easily fail (and has failed for me), and isn't necessary anyway. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Xiaojie Yuan authored
Fix the NULL pointer dereference while running amdgpu_test: [ 54.972246] BUG: unable to handle kernel NULL pointer dereference at 0000000000000000 [ 54.972265] IP: (null) [ 54.972273] PGD 0 P4D 0 [ 54.972280] Oops: 0010 [#1] SMP PTI [ 54.972288] Modules linked in: amdkfd amd_iommu_v2 amdgpu(OE) chash gpu_sched ttm drm_kms_helper drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect sysimgblt snd_hda_codec_realtek snd_hda_codec_generic snd_hda_codec_hdmi snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep intel_rapl snd_pcm snd_seq_midi snd_seq_midi_event snd_rawmidi x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel snd_seq snd_seq_device kvm irqbypass snd_timer crct10dif_pclmul crc32_pclmul ghash_clmulni_intel pcbc snd soundcore joydev input_leds aesni_intel aes_x86_64 crypto_simd glue_helper cryptd idma64 virt_dma mei_me intel_lpss_pci serio_raw intel_cstate intel_rapl_perf shpchp intel_pch_thermal mei mac_hid intel_lpss acpi_pad parport_pc ppdev nfsd lp auth_rpcgss nfs_acl lockd grace sunrpc parport autofs4 hid_generic [ 54.972434] usbhid mxm_wmi e1000e psmouse ahci hid libahci wmi pinctrl_sunrisepoint video pinctrl_intel [ 54.972457] CPU: 6 PID: 1393 Comm: uvd Tainted: G OE 4.16.0-rc7-27fb84fda777 #1 [ 54.972473] Hardware name: MSI MS-7984/Z170 KRAIT GAMING (MS-7984), BIOS B.80 05/11/2016 [ 54.972489] RIP: 0010: (null) [ 54.972497] RSP: 0018:ffffaea002c8bcc0 EFLAGS: 00010202 [ 54.972508] RAX: 0000000000000000 RBX: ffff9d30d3c56f60 RCX: 00000000007c0002 [ 54.972522] RDX: 000000000001a6fb RSI: 000000000001a6e9 RDI: ffff9d30d3c56f60 [ 54.972536] RBP: ffffaea002c8bd10 R08: 0000000000000002 R09: ffffffffc06977d0 [ 54.972550] R10: 0000000000000040 R11: 0000000000000000 R12: 0000000000000002 [ 54.972564] R13: ffff9d30d3c5001c R14: ffff9d30d3c50000 R15: 0000000000000006 [ 54.972579] FS: 0000000000000000(0000) GS:ffff9d30eed80000(0000) knlGS:0000000000000000 [ 54.972594] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 54.972606] CR2: 0000000000000000 CR3: 00000002dbc0a001 CR4: 00000000003606e0 [ 54.972620] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 54.972634] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 54.972648] Call Trace: [ 54.972685] ? gmc_v9_0_emit_flush_gpu_tlb+0x111/0x140 [amdgpu] [ 54.972721] uvd_v7_0_ring_emit_vm_flush+0x31/0x70 [amdgpu] [ 54.972751] amdgpu_vm_flush+0x5dc/0x6c0 [amdgpu] [ 54.972787] ? pp_dpm_powergate_uvd+0x50/0x80 [amdgpu] [ 54.972816] amdgpu_ib_schedule+0x120/0x4e0 [amdgpu] [ 54.972850] amdgpu_job_run+0x17b/0x1c0 [amdgpu] [ 54.972861] drm_sched_main+0x2cc/0x490 [gpu_sched] [ 54.972873] ? wait_woken+0x80/0x80 [ 54.972882] kthread+0x121/0x140 [ 54.972891] ? drm_sched_job_finish+0xf0/0xf0 [gpu_sched] [ 54.972902] ? kthread_create_worker_on_cpu+0x70/0x70 [ 54.972914] ret_from_fork+0x35/0x40 [ 54.972922] Code: Bad RIP value. [ 54.972932] RIP: (null) RSP: ffffaea002c8bcc0 [ 54.972943] CR2: 0000000000000000 [ 54.972951] ---[ end trace 5feb349263bbf633 ]--- Signed-off-by:
Xiaojie Yuan <Xiaojie.Yuan@amd.com> Reviewed-by:
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Harry Wentland authored
The two ranges overlap. Signed-off-by:
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Harry Wentland authored
Signed-off-by:
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Jerry (Fangzhi) Zuo authored
Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Harry Wentland authored
Signed-off-by:
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Harry Wentland authored
Things such as mis-indent, and space at beginning of line. Signed-off-by:
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Harry Wentland authored
We are not sure these calculations will never need negative numbers. Use signed integers and warn and cap at 0 if this ever happens. Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Tony Cheng authored
Signed-off-by:
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Martin Tsai authored
Signed-off-by:
Martin Tsai <Martin.Tsai@amd.com> Reviewed-by:
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Jerry (Fangzhi) Zuo authored
Extended fix to: "Don't read EDID in atomic_check" Fix issue of missing dc_sink in .mode_valid in hot plug routine. Need to check dc_sink everytime in .get_modes hook after checking edid, since edid is not getting removed in hot unplug but dc_sink doesn't. Signed-off-by:
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Julian Parkin authored
To ensure the infoframe gets updated during an SDR/HDR switch this change adds a new function to to check if the HDR static metadata has changed and adds it to is_timing_changed and pipe_need_reprogram checks Signed-off-by:
Julian Parkin <jparkin@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Jerry (Fangzhi) Zuo authored
Extended fix to: "Don't read EDID in atomic_check" Fix display property not observed in GUI display after hot plug. Call drm_mode_connector_update_edid_property every time in .get_modes hook, due to the fact that edid property is getting removed from usermode ioctl DRM_IOCTL_MODE_GETCONNECTOR each time in hot unplug. Signed-off-by:
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Julian Parkin authored
Signed-off-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Krunoslav Kovac authored
Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Tony Cheng authored
Signed-off-by:
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Hersen Wu authored
remove limit YUV422 color depth to 24bits which is workaround for old ASIC Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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Eric Bernstein authored
Also rename otg_blank to blank_pixel_data. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Eric Bernstein authored
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Anthony Koo authored
Check in code was incorrect, and infopacket is only transmitted after update function is called multiple times. Purpose of the function was to check if infopackets are being enabled, and then enable global control. Fix the code to do this. Signed-off-by:
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Harry Wentland authored
The below commit "drm/atomic: Try to preserve the crtc enabled state in drm_atomic_remove_fb, v2" introduces a slight behavioral change to rmfb. Instead of disabling a crtc when the primary plane is disabled, it now preserves it. Since DC is currently not equipped to handle this we need to fail such a commit, otherwise we might see a corrupted screen. This is based on Shirish's previous approach but avoids adding all planes to the new atomic state which leads to a full update in DC for any commit, and is not what we intend. Theoretically DM should be able to deal with states with fully populated planes, even for simple updates, such as cursor updates. This should still be addressed in the future. Signed-off-by: -
Mikita Lipski authored
Merge amdgpu_dm_display_resume function into dm_resume, as it is not called anywhere else anymore. Initially the call was broken down into 2 functions for cursor corruption issue. Now the issue is not visible, hence the dm_resume will perform dm_display_resume in it. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Mikita Lipski authored
Lock irq table when reading a work in queue, unlock to flush the work, lock again till all tasks are cleared Signed-off-by:
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Emily Deng authored
After host os reset gpu reset, need to set flag in_gpu_reset to zero. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Emily Deng authored
When put the IB test out of exclusive mode, and do sriov reset, the IB test will randomly fail. As out of exclusive mode it uses kiq to do read and write registers, but as it has world switch, the kiq read and write time will be random, sometimes it will beyond the MAX_KIQ_REG_WAIT and then the read or write register will fail, which will result the IB test fail. Signed-off-by:
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Pixel Ding authored
The current sequence in scheduler thread is: 1. update last sched fence 2. job begin (adding to mirror list) 3. job finish (remove from mirror list) 4. back to 1 Since we update last sched prior to joining mirror list, the jobs in mirror list already pass the last sched fence. TDR just run the jobs in mirror list, so we should not update the last sched fences in TDR. Signed-off-by:
Pixel Ding <Pixel.Ding@amd.com> Reviewed-by:
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Eric Huang authored
Add the powertune table for VEGAM. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by:
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Eric Huang authored
VEGAM specific changes for smu7: 1. add avfs control. 2. add a smc message defferent as smu7. 3. don't switch mc arb memory timing. 4. update LCAC_MC0/1_CNTL value. Signed-off-by:
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Eric Huang authored
The smumgr handles communication between the driver and the SMU for power management. v2: fix typo (Alex) Signed-off-by:
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Eric Huang authored
Add functionality to fetch gpio table from vbios. Signed-off-by:
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Eric Huang authored
used for calculating memory clocks in powerplay. v2: handle endian swapping of atom data (Alex) Signed-off-by:
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Eric Huang authored
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Eric Huang authored
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Harry Wentland authored
Some eDP displays use the extra link rate table to advertise link rate support. If they do that they don't need to provide link rate through the usual registers. Since we don't currently have support for the extra link rate table default to HBR2 for the display in this. Note that this is a HACK. Ultimately we need to teach DC to use the extra link rate table. Signed-off-by:
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Alex Deucher authored
DC is preferred. Signed-off-by:
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