An error occurred fetching the project authors.
- 05 Jan, 2016 1 commit
-
-
Linus Walleij authored
This makes the driver use the data pointer added to the gpio_chip to store a pointer to the state container instead of relying on container_of(). Cc: Chen-Yu Tsai <wens@csie.org> Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
-
- 26 Dec, 2015 1 commit
-
-
Linus Walleij authored
As we want gpio_chip .get() calls to be able to return negative error codes and propagate to drivers, we need to go over all drivers and make sure their return values are clamped to [0,1]. We do this by using the ret = !!(val) design pattern. Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
-
- 19 Nov, 2015 1 commit
-
-
Linus Walleij authored
The name .dev in a struct is normally reserved for a struct device that is let us say a superclass to the thing described by the struct. struct gpio_chip stands out by confusingly using a struct device *dev to point to the parent device (such as a platform_device) that represents the hardware. As we want to give gpio_chip:s real devices, this is not working. We need to rename this member to parent. This was done by two coccinelle scripts, I guess it is possible to combine them into one, but I don't know such stuff. They look like this: @@ struct gpio_chip *var; @@ -var->dev +var->parent and: @@ struct gpio_chip var; @@ -var.dev +var.parent and: @@ struct bgpio_chip *var; @@ -var->gc.dev +var->gc.parent Plus a few instances of bgpio that I couldn't figure out how to teach Coccinelle to rewrite. This patch hits all over the place, but I *strongly* prefer this solution to any piecemal approaches that just exercise patch mechanics all over the place. It mainly hits drivers/gpio and drivers/pinctrl which is my own backyard anyway. Cc: Haavard Skinnemoen <hskinnemoen@gmail.com> Cc: Rafał Miłecki <zajec5@gmail.com> Cc: Richard Purdie <rpurdie@rpsys.net> Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Cc: Alek Du <alek.du@intel.com> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Takashi Iwai <tiwai@suse.com> Acked-by:
Dmitry Torokhov <dmitry.torokhov@gmail.com> Acked-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by:
Lee Jones <lee.jones@linaro.org> Acked-by:
Jiri Kosina <jkosina@suse.cz> Acked-by:
Hans-Christian Egtvedt <egtvedt@samfundet.no> Acked-by:
Jacek Anaszewski <j.anaszewski@samsung.com> Signed-off-by:
-
- 23 Oct, 2015 1 commit
-
-
Hans de Goede authored
The r_pio gpio / pin controller has a pin_base of non 0, we need to adjust for this before calling sunxi_pinctrl_desc_find_function_by_pin. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Acked-by:
-
- 16 Oct, 2015 1 commit
-
-
Jonas Gorski authored
Replace all trivial request/free callbacks that do nothing but call into pinctrl code with the generic versions. Signed-off-by:
Jonas Gorski <jogo@openwrt.org> Acked-by:
Bjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by:
Heiko Stuebner <heiko@sntech.de> Acked-by:
Eric Anholt <eric@anholt.net> Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by:
Andrew Bresticker <abrestic@chromium.org> Acked-by:
Baruch Siach <baruch@tkos.co.il> Acked-by:
Matthias Brugger <matthias.bgg@gmail.com> Acked-by:
Lee Jones <lee@kernel.org> Acked-by:
Laxman Dewangan <ldewangan@nvidia.com> Acked-by:
-
- 02 Oct, 2015 1 commit
-
-
Javier Martinez Canillas authored
It's not needed an is just creating a null statement, so remove it. Signed-off-by:
Javier Martinez Canillas <javier@osg.samsung.com> Acked-by:
-
- 16 Sep, 2015 2 commits
-
-
Thomas Gleixner authored
Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by:Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
-
Thomas Gleixner authored
__irq_set_chip_handler_name_locked() is about to be replaced. Use irq_set_chip_handler_name_locked() instead. Signed-off-by:
-
- 27 Jul, 2015 3 commits
-
-
Maxime Ripard authored
The current interrupt parsing code was working by accident, because the default was actually parsing the first node of interrupts. While that was mostly working (and the flags were actually ignored), this binding has never been documented, and doesn't work with SoCs that have multiple interrupt banks anyway. Add a proper interrupt xlate function, that uses the same description than the GPIOs (<bank> <pin> <flags>), that will make things less confusing. The EINT number will still be used as the hwirq number, but won't be exposed through the DT. Signed-off-by:
-
Maxime Ripard authored
In order to ease the debugging, add a name to the irq_chips. Signed-off-by:
-
Maxime Ripard authored
The current code uses some custom variable affectations, while we have common functions to do exactly that. Move to the common functions. Signed-off-by:
-
- 17 Jul, 2015 2 commits
-
-
Thomas Gleixner authored
The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: -
Jiang Liu authored
Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we already have a pointer to corresponding irq_desc. Signed-off-by:
Jiang Liu <jiang.liu@linux.intel.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by:
-
- 25 Jun, 2015 1 commit
-
-
Thomas Gleixner authored
Fix a race where a pending interrupt could be received and the handler called before the handler's data has been setup, by converting to irq_set_chained_handler_and_data(). Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); | -irq_set_chained_handler(E1, E3); ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); ... | -irq_set_chained_handler(E1, E3); ... ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by:
Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by:
-
- 10 Jun, 2015 1 commit
-
-
Masahiro Yamada authored
Currently, pinctrl_register() just returns NULL on error, so the callers can not know the exact reason of the failure. Some of the pinctrl drivers return -EINVAL, some -ENODEV, and some -ENOMEM on error of pinctrl_register(), although the error code might be different from the real cause of the error. This commit reworks pinctrl_register() to return the appropriate error code and modifies all of the pinctrl drivers to use IS_ERR() for the error checking and PTR_ERR() for getting the error code. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by:
Patrice Chotard <patrice.chotard@st.com> Acked-by:
Thierry Reding <treding@nvidia.com> Acked-by:
Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by:
Ray Jui <rjui@broadcom.com> Acked-by:
Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by:
Hongzhou Yang <hongzhou.yang@mediatek.com> Acked-by:
Wei Chen <Wei.Chen@csr.com> Signed-off-by:
-
- 18 Mar, 2015 1 commit
-
-
Hans de Goede authored
On sun4i-a10, when GPIOs are configured as external interrupt the value for them in the data register does not seem to get updated, so set their mux to input (and restore afterwards) when reading the pin. Missed edges seem to be buffered, so this does not introduce a race condition. I've also tested this on sun5i-a13 and sun7i-a20 and those do not seem to be affected, the input value representation in the data register does seem to correctly get updated to the actual pin value while in irq mode there. Signed-off-by:
-
- 28 Oct, 2014 1 commit
-
-
Alexandre Courbot authored
This function actually operates on a gpio_chip, so its prefix should reflect that fact for consistency with other functions defined in gpio/driver.h. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
-
- 04 Sep, 2014 1 commit
-
-
Linus Walleij authored
commit 2243a87d "pinctrl: avoid duplicated calling enable_pinmux_setting for a pin" removed the .disable callback from the struct pinmux_ops, making the .enable() callback the only remaining callback. However .enable() is a bad name as it seems to imply that a muxing can also be disabled. Rename the callback to .set_mux() and also take this opportunity to clean out any remaining mentions of .disable() from the documentation. Acked-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Fan Wu <fwu@marvell.com> Signed-off-by:
-
- 28 Jul, 2014 2 commits
-
-
Chen-Yu Tsai authored
The pinctrl-sunxi driver originally used the pin number as the gpio range offset. This resulted in large, bogus gpio numbers for the new sun6i-a31-r pinctrl devices. This patch makes the driver number the gpios ranges starting from an offset of 0, by subtracting the pin_base number from the pin number. This also makes the system-wide gpio number match the pin number. Tested on sun8i with sysfs exported gpios. This patch also changes the GPIO bindings for R_PIO: gpios = <&r_pio B N flag>; Where B originally was the pinbank label (L or M) counted from A, with this patch it becomes (L or M) counted from its pinbank base (L). Thus gpios = <&r_pio 10 11 0>; /* PL11 */ becomes gpios = <&r_pio 0 11 0>; /* PL11 */ IMO this is correct, as the binding shows the bank offset and pin offset within the bank for the GPIO controller. But I'm worried it might be a bit confusing. Signed-off-by: -
Chen-Yu Tsai authored
When an IRQ is started on a GPIO line, mark this GPIO as IRQ in the gpiolib so we can keep track of the usage centrally. Signed-off-by:
-
- 22 Jul, 2014 1 commit
-
-
abdoulaye berthe authored
Signed-off-by:
abdoulaye berthe <berthe.ab@gmail.com> Signed-off-by:
-
- 11 Jul, 2014 5 commits
-
-
Chen-Yu Tsai authored
When mapping the interrupts, the gpio_to_irq function did not consider the bank number of the gpio pin in question, only the offset or the interrupt number in the bank. As a result, requests for interrupts in the later banks get mapped to the first bank. This issue was discovered while enabling mmc on the new sun8i platform. The tablet I have uses a pin/interrupt from the second bank to do mmc card detection. Tested on this very device with register inspection and actual mmc card insertion/removal. Signed-off-by:
-
Hans de Goede authored
Some drivers use disable_irq / enable_irq and do the work clearing the source in another thread instead of using a threaded interrupt handler. The irqchip used not having irq_disable and irq_enable callbacks in this case, will lead to unnecessary spurious interrupts: On a disable_irq in a chip without a handler for this, the irq core will remember the disable, but not actually call into the irqchip. With a level triggered interrupt (where the source has not been cleared) this will lead to an immediate retrigger, at which point the irq-core will mask the irq. So having an irq_disable callback in the irqchip will save us the interrupt firing a 2nd time for nothing. Drivers using disable / enable_irq like this, will call enable_irq when they finally have cleared the interrupt source, without an enable_irq callback, this will turn into an unmask, at which point the irq will trigger immediately because when it was originally acked the level was still high, so the ack was a nop. Signed-off-by:
-
Hans de Goede authored
For level triggered gpio interrupts we need to use handle_fasteoi_irq, like we do with the irq-sunxi-nmi driver. This is necessary to give threaded interrupt handlers a chance to actuall clear the source of the interrupt (which may involve sleeping waiting for i2c / spi / mmc transfers), before acknowledging the interrupt. Signed-off-by:
-
Hans de Goede authored
With level triggered interrupt mask / unmask will get called for each interrupt, doing the somewhat expensive mux setting on each unmask thus is not a good idea. Instead add a request_resources callback and do it there. Signed-off-by:
-
Chen-Yu Tsai authored
The sunxi pinctrl irq chip driver does not support wakeup at the moment. Adding IRQCHIP_SKIP_SET_WAKE lets the irqs work with drivers using wakeup. Signed-off-by:
-
- 19 Jun, 2014 3 commits
-
-
Maxime Ripard authored
The A23 and A31 support multiple interrupt banks. Support it by adding a linear domain covering all the banks. It's trickier than it should because there's an interrupt per bank, so we have multiple interrupts using the same domain. Signed-off-by:
-
Maxime Ripard authored
If irq_mask_ack is not defined, mask_ack_irq will call irq_mask and then irq_ack. In order to avoid code duplication, between irq_mask_ack and irq_mask, just declare irq_ack. Signed-off-by:
-
Sachin Kamat authored
kzalloc can fail. Add a null check to avoid null pointer dereference error while accessing the pointer later. Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Acked-by:
-
- 27 May, 2014 2 commits
-
-
Chen-Yu Tsai authored
The irq/pin mapping is used to lookup the pin to mux to the irq function when the irq is enabled. It is created when gpio_to_irq is called. Creating the mapping during init allows us to map the interrupts directly from the device tree. Originally the IRQ to pin mapping was created when gpio_to_irq was called with a GPIO handle. The mapping in turn is used to mux the pin into EINT mode. If the mapping is created during gpio_to_irq, we can't use the interrupts directly, i.e. through the DT with "interrupts = <&pio A 4>". Instead we'd have to use "gpios = <&pio A B>", then pass the gpio through to gpio_to_irq. Signed-off-by:
-
Chen-Yu Tsai authored
The pin numbers passed to sunxi_*_reg helpers to get the correct registers should be the pin offset for the PIO block, not the absolute number we use that is based on the alphanumeric labels Allwinner uses. This patch subtracts .pin_base from the pin number passed to these functions, so the driver accesses the correct registers. Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by:
-
- 22 May, 2014 1 commit
-
-
Maxime Ripard authored
When the support for the PRCM muxer on the A31 has been added, the global static pinctl_desc definition has been left as is. Unfortunately, this structure is used to register the pinctrl device, and prior to this registration, we set the name and pins field. Since this structure is shared across instances, that means that the latest registered pinctrl device wins in setting the name, pins and pins numbers, which is not really a good thing. Signed-off-by:
-
- 05 May, 2014 1 commit
-
-
Maxime Ripard authored
The way that reset is handled right now is that it is made optional for every pinctrl driver, while actually, it isn't used at all for the main pin controllers so far, and while it's mandatory for the A31's secondary pin controller. Move the reset functions out of the core and in the driver, where they can be made mandatory. Signed-off-by:
-
- 04 May, 2014 7 commits
-
-
Maxime Ripard authored
Move the pin description to a driver specific to be. This is the final step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. We can finally remove that header, and remove all the driver part of the pinctrl-sunxi core. Signed-off-by: -
Maxime Ripard authored
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: -
Maxime Ripard authored
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: -
Maxime Ripard authored
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: -
Maxime Ripard authored
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: -
Maxime Ripard authored
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: -
Maxime Ripard authored
This will allow to have multiple drivers using the same core code, and eventually, retire pinctrl-sunxi-pins.h Signed-off-by:
-
