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- 10 Jan, 2024 1 commit
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Mika Kahola authored
Add pll selection check for C20 as well as clock state verification0. We have been relying on sw state to select A or B pll's. This is incorrect as the hw might see this selection differently. This patch fixes this shortcoming by reading pll selection for both sw and hw states and compares if these two selections match. Fixes: 59be9024 ("drm/i915/mtl: C20 state verification") v2: reword commit message and include fix to a original commit (Imre) Compare pll selection (Jani) Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Reviewed-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240102115741.118525-2-mika.kahola@intel.com (cherry picked from commit f4304bea) Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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- 18 Dec, 2023 1 commit
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Imre Deak authored
Select the HDMI specific PLL clock only for HDMI outputs. Fixes: 62618c7f ("drm/i915/mtl: C20 PLL programming") Cc: Mika Kahola <mika.kahola@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com>
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- 15 Dec, 2023 1 commit
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Imre Deak authored
Select the HDMI specific PLL clock only for HDMI outputs. Fixes: 62618c7f ("drm/i915/mtl: C20 PLL programming") Cc: Mika Kahola <mika.kahola@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by:
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- 08 Dec, 2023 3 commits
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Radhakrishna Sripada authored
With the cleanup of the misleading clock value to avoid extra calculations to convert between link_bit_rate and clock, use one standard "clock" field for the c20 pll which works with crtc_state->port_clock field. Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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Radhakrishna Sripada authored
The field link_bit_rate serves as the actual clock value for the C20 pll_state structure. Remove the misleading clock field. The subsequent patch would rename the link_bit_rate as the clock field. Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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Radhakrishna Sripada authored
In C20 pll_state link_bit_rate and clock fields are bit redundant. Since many of the helpers assume the clock values, which are different from link_bit_rate for dp2.0, convert the helpers to use the numbers that are compatible with link_bit_rate. Currently link_bit_rate is compatible with crtc_state->port_clock. The function intel_c20pll_calc_port_clock returns the number which is compatible with crtc_state->port_clock. In order to avoid extra conversions b/ween clock and link_bit_rate, remove "clock" field from the C20 pll_state and then rename "link_bit_rate" as "clock". While at it rely on crtc_state->port_clock during C20 Pll programming. Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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- 01 Dec, 2023 1 commit
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Mika Kahola authored
With TBT-ALT mode we are not programming C20 chip PLL's and hence we don't need to check state verification. We don't need to program DP link signal levels i.e.pre-emphasis and voltage swing either. This patch fixes dmesg errors like this one "[drm] ERROR PHY F Write 0c06 failed after 3 retries." Signed-off-by:
Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231129122221.1109084-1-mika.kahola@intel.com
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- 13 Nov, 2023 1 commit
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Mika Kahola authored
Add state verification for C20 as we have one for C10. V2: Use abstractation of HW readout (Gustavo) Drop MPLLA/B from message for TX and CMN parameters (Gustavo) Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> (v1,v2) Signed-off-by:
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- 29 Oct, 2023 3 commits
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Lucas De Marchi authored
As done with the hw readout, properly abstract the C10/C20 phy details inside intel_cx0_phy.c. Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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Lucas De Marchi authored
intel_cx0_phy.[ch] should contain the details about C10/C20, not leaking it to the rest of the driver. Start abstracting this by exporting a single PLL hw readout that handles the differences between C20 and C10 internally to that compilation unit. Signed-off-by:
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Lucas De Marchi authored
For Lunar Lake, DDI-A is connected to C10 PHY, while TC1-TC3 are connected to C20 phy, like in Meteor Lake. Update the check in intel_is_c10phy() accordingly. This reverts the change in commit e388ae97 ("drm/i915/display: Eliminate IS_METEORLAKE checks") that turned that into a display engine version check. The phy <-> port connection is very SoC-specific and not related to that version. IS_LUNARLAKE() is defined to 0 in i915 as it's expected that the (upcoming) xe driver is the one defining the platform, with i915 only driving the display side. Bspec: 70818 Reviewed-by:
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- 26 Oct, 2023 1 commit
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Mika Kahola authored
Every know and then we receive the following error when running for example IGT test kms_flip. [drm] *ERROR* PHY G Read 0d80 failed after 3 retries. [drm] *ERROR* PHY G Write 0d81 failed after 3 retries. Since the error is sporadic in nature, the patch proposes to reset the message bus after every successful or unsuccessful read or write operation. v2: Add FIXME's to indicate the experimental nature of this workaround (Rodrigo) v3: Dropping the additional delay as moving reset to *_read_once() and *_write_once() functions seem unnecessary delay Signed-off-by:Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231016125544.719963-1-mika.kahola@intel.com
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- 18 Oct, 2023 1 commit
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Khaled Almahallawy authored
Currently, with MFD/pin assignment D, the driver clears the pipe reset bit of lane 1 which is not owned by display. This causes the display to block S0iX. By not clearing this bit for lane 1 and keeping whatever default, S0ix started to work. This is already what the driver does at the end of the phy lane reset sequence (Step#8) Bspec: 65451 Fixes: 619a06db ("drm/i915/mtl: Reset only one lane in case of MFD") Cc: Mika Kahola <mika.kahola@intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by:
Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by:
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- 16 Oct, 2023 1 commit
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Ville Syrjälä authored
Just use a simple {} to zero initialize arrays/structs instead of the hodgepodge of stuff we are using currently. Signed-off-by:Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231012122442.15718-2-ville.syrjala@linux.intel.comReviewed-by:
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- 11 Oct, 2023 1 commit
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Khaled Almahallawy authored
Currently, with MFD/pin assignment D, the driver clears the pipe reset bit of lane 1 which is not owned by display. This causes the display to block S0iX. By not clearing this bit for lane 1 and keeping whatever default, S0ix started to work. This is already what the driver does at the end of the phy lane reset sequence (Step#8) Bspec: 65451 Fixes: 619a06db ("drm/i915/mtl: Reset only one lane in case of MFD") Cc: Mika Kahola <mika.kahola@intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by:
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- 06 Oct, 2023 2 commits
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Ville Syrjälä authored
Passing in the atomic state + crtc state is a bit weird. The latter can be just the crtc (which is the normal calling convention used in a lot of other places). Signed-off-by:
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Ville Syrjälä authored
State checkers should never modify the crtc states, so make them const. Signed-off-by:
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- 18 Sep, 2023 1 commit
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Gustavo Sousa authored
There was a recent update in the BSpec adding an extra step to the PLL enable sequence, which is for programming the msgbus timer. Since we also touch PHY registers during hw readout, let's do the programming when starting a transaction rather than only when doing the PLL enable sequence. This might be the missing step that was causing the timeouts that we have recently seen during C20 SRAM register programming sequences. With this in place, we shouldn't need the logic to bump the timer thresholds, since now we have a documented value that should be set peform programming the registers. As such, let's also remove intel_cx0_bus_check_and_bump_timer(), but keep the part that checks if hardware really detected a timeout, which might be useful debugging information. v2: - Use debug level instead of warning for the message notifying that the hardware did not detect the timeout. (Mika) - Got a new BSpec update clarifying that we need to program the msgbus timer of both PHY lanes. Update the changes to reflect that. (Gustavo) BSpec: 64568 Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230912155923.39494-1-gustavo.sousa@intel.com
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- 06 Sep, 2023 2 commits
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Gustavo Sousa authored
We have experienced timeout issues when going through the sequence to access C20 SRAM registers. Experimentation showed that bumping the message bus timer threshold helped on getting display Type-C connection on the C20 PHY to work. While the timeout is still under investigation with the HW team, having logic to allow forward progress (with the proper warnings) seems useful. Thus, let's bump the threshold when a timeout is detected. The bumped value of 0x200 pclk cycles was somewhat arbitrary - 2x the default value. That value was successfully tested on real hardware that was displaying timeouts otherwise. v2: - Reword commit message to indicate that access to C20 SRAM registers is not direct. (Radhakrishna) - Prefer not to use REG_FIELD_PREP() in intel_cx0_phy.c. (Radhakrishna) - Simplify intel_cx0_bus_check_and_bump_timer() to use a fixed bumped value instead of progressively increasing the threshold. (Mika) BSpec: 65156 Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: -
Luca Coelho authored
It is irrelevant for the caller that the max lane count is being derived from a FIA register, so having "fia" in the function name is irrelevant. Rename the function accordingly. Reviewed-by:
Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by:
Luca Coelho <luciano.coelho@intel.com> Signed-off-by:
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- 22 Aug, 2023 1 commit
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Matt Roper authored
Most of the IS_METEORLAKE checks in the display code shouldn't actually be tied to MTL as a platform, but rather to the Xe_LPD+ display IP (which is used in MTL, but may show up again in future platforms). In cases where we're trying to match that specific IP, use a version check against IP_VER(14, 0). For cases where we're just handling new behavior introduced by this IP (but which may also be inherited by future IP as well), use a ver >= 14 check. The one exception here is the stolen memory workaround Wa_13010847436 (which is mislabelled as "Wa_22018444074" in the code). That's truly a MTL-specific issue rather than being tied to any of the IP blocks, so leaving the condition as IS_METEORLAKE is correct there. v2: - cdclk check should be >=, not >. (Gustavo) Signed-off-by:
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- 17 Aug, 2023 4 commits
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Gustavo Sousa authored
According to the BSpec, voltage swing programming should be done for owned PHY lanes. Do not program a not-owned PHY lane. BSpec: 74103, 74104 Reviewed-by:
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Gustavo Sousa authored
Display must not enable or disable transmitters for not-owned PHY lanes. BSpec: 64539 Reviewed-by:
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Gustavo Sousa authored
It is possible to generalize the "disable" value for the transmitters to be a bit mask based on the port width and the port reversal boolean, with a small exception for DP-alt mode with "x1" port width. Simplify the code by using such a mask and a for-loop instead of using switch-case statements. v2: - Use (i < 2) instead of (i / 2 == 0) for PHY lane mask selection. (Jani) BSpec: 64539 Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: -
Gustavo Sousa authored
There are more parts of C10/C20 programming that need to take owned lanes into account. Define the function intel_cx0_get_owned_lane_mask() and use it. There will be new users of that function in upcoming changes. BSpec: 64539 Reviewed-by:
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- 26 Jun, 2023 1 commit
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Radhakrishna Sripada authored
Driver does not clear the default SSC for MPLLA. This causes link training failure when trying to use 10G and 20G rates. Fix the behaviour and enable ssc only when we really want. Fixes: 237e7be0 ("drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA") Cc: Mika Kahola <mika.kahola@intel.com> Cc: Clint Taylor <Clinton.A.Taylor@intel.com> Cc: Khaled Almahallawy <khaled.almahallawy@intel.com> Cc: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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- 20 Jun, 2023 1 commit
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Radhakrishna Sripada authored
Driver does not clear the default SSC for MPLLA. This causes link training failure when trying to use 10G and 20G rates. Fix the behaviour and enable ssc only when we really want. Fixes: 237e7be0 ("drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA") Cc: Mika Kahola <mika.kahola@intel.com> Cc: Clint Taylor <Clinton.A.Taylor@intel.com> Cc: Khaled Almahallawy <khaled.almahallawy@intel.com> Cc: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by:
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- 15 Jun, 2023 1 commit
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Mika Kahola authored
From PICA message bus we wait for acknowledgment from read/write commands. In case of an error, we reset the bus for the next command. Current implementation ends up resetting message bus twice in cases where error is not the timeout. Since, we only need to reset message bus once, let's move reset to corresponding timeout error and drop the excess reset function calls from read/write functions. Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230609122130.69794-1-mika.kahola@intel.com
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- 05 Jun, 2023 1 commit
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Mika Kahola authored
In case when only two or less transmit lanes are owned such as MFD (DP-alt with x2 lanes) we need to reset only one data lane (lane0). With only x2 lanes we don't need to poll for the phy current status on both data lanes since only the owned data lane will respond. v2: Find better naming for lanes and revise the commit message (Luca) Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> (v1) Signed-off-by:
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- 19 May, 2023 1 commit
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Clint Taylor authored
Use algorithm to generate HDMI C20 PLL clock frequencies. v2: checkpatch fixes BSPEC: 64568 Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by:
Clint Taylor <clinton.a.taylor@intel.com> [mattrope: Wrapped one overly long line] Signed-off-by:
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- 18 May, 2023 1 commit
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Mika Kahola authored
While disabling Thunderbolt PLL, we request PLL to be stopped and wait for ACK bit to be cleared. The expected value should be '0' instead of '~XELPDP_TBT_CLOCK_ACK' or otherwise we incorrectly receive dmesg warn "PHY PLL not unlocked in 10us". Signed-off-by:
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- 15 May, 2023 1 commit
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Jani Nikula authored
Add i915 parameter to I915_STATE_WARN() and use device based logging. Done using cocci + hand edited where there was no i915 local variable ready. v2: avoid null deref in verify_connector_state() Reviewed-by:
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- 28 Apr, 2023 8 commits
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Mika Kahola authored
Add register writes to enable powering up Type-C subsystem i.e. TCSS. For MeteorLake we need to request TCSS to power up and check the TCSS power state after 500 us. In addition, for PICA we need to set/clear the Type-C PHY ownnership bit when Type-C device is connected/disconnected. Reviewed-by:
Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
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Mika Kahola authored
Readout hw state for Thunderbolt. Reviewed-by:
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Mika Kahola authored
Enabling and disabling sequence for Thunderbolt PLL. Bspec: 64568 v2: Use intel_de_wait_for_register() (RK) Reviewed-by:
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Mika Kahola authored
Use MPLLA for DP2.0 rates 10G and 20G, when ssc is enabled. v2: Fix typo in commit message (Animesh) Reviewed-by:
Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by:
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Mika Kahola authored
Calculate port clock with C20 phy. BSpec: 64568 Reviewed-by:
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Mika Kahola authored
As we already do with C10 chip, let's dump the pll hw state for C20 as well. Reviewed-by:
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Mika Kahola authored
Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates. The PLL settings are based on table, not for algorithmic alternative. For DP 1.4 only MPLLB is in use. Once register settings are done, we read back C20 HW state. BSpec: 64568 v2: Updated pll tables (RK) MPLLB selection fix (RK) Signed-off-by:Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by:
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Mika Kahola authored
C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add 4 lane support for c20. v2: Add 6.48Gbps and 6.75Gbps modes for eDP (RK) Fix lane check (RK) Fix multiline commenting (Arun) use usleep_range() instead of msleep() (Andi) Reviewed-by:José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
Bhanuprakash Modem <bhanuprakash.modem@intel.com> Signed-off-by:
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