- 26 Jul, 2012 5 commits
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Timur Tabi authored
In order for indirect mode on the PIXIS to work properly, both chip selects need to be set to GPCM mode, otherwise writes to the chip select base addresses will not actually post to the local bus -- they'll go to the NAND controller instead. Therefore, we need to set BR0 and BR1 to GPCM mode before switching to indirect mode. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Timur Tabi authored
The Freescale P1022 has a unique pin muxing "feature" where the DIU video controller's video signals are muxed with 24 of the local bus address signals. When the DIU is enabled, the bulk of the local bus is disabled, preventing access to memory-mapped devices like NAND flash and the pixis FPGA. Therefore, if the DIU is going to be enabled, then memory-mapped devices on the localbus, like NAND flash, need to be disabled. This patch is similar to "powerpc/85xx: p1022ds: disable the NOR flash node if video is enabled", except that it disables the NAND flash node instead. This PIXIS node needs to remain enabled because it is used by platform code to switch into indirect mode. Signed-off-by:
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Claudiu Manoil authored
The sram_offset parameter represents a physical address and should be of type phys_addr_t. As part of this fix, the extraction of sram_params is being cleaned-up and fixed. This patch fixes now the case when the offset value of 0xfff00000 was being rejected by the driver (returning -EINVAL), although this is a valid offset value. Signed-off-by:
Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by:
Claudiu Manoil <claudiu.manoil@freescale.com> Signed-off-by:
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Shaohui Xie authored
Default CoreNet Coherency Bus (CCB) frequency on P3041 is 750MHz, but espi cannot work at 40MHz with this CCB frequency, so we need to slow down the clock rate of espi to 35MHz to make it work stable at the CCB frequency. Signed-off-by:
Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by:
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Tang Yuantian authored
Signed-off-by:
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- 23 Jul, 2012 1 commit
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Benjamin Herrenschmidt authored
The current mpic code creates a linear revmap just big enough for all the sources, which happens to miss the IPIs and timers on some machines. This will in turn break when the irqdomain code loses the fallback of doing a linear search when the revmap fails (and really slows down IPIs otherwise). This happens for example on the U4 based Apple machines such as the dual core PowerMac G5s. Signed-off-by:Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- 22 Jul, 2012 1 commit
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Benjamin Herrenschmidt authored
Commit 9778b696 accidentally added a .rej file (probably my fault), remove it. Signed-off-by:
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- 13 Jul, 2012 3 commits
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Benjamin Herrenschmidt authored
The iommu pool patch has a bug where it would cause a crash when using only one pool (based on the size of the DMA window). Signed-off-by: -
Benjamin Herrenschmidt authored
Freescale updates for 3.6
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Kleber Sacilotto de Souza authored
Function eeh_event_handler() dereferences the pointer returned by handle_eeh_events() without checking, causing a crash if NULL was returned, which is expected in some situations. This patch fixes this bug by checking for the value returned by handle_eeh_events() before dereferencing it. Signed-off-by:
Kleber Sacilotto de Souza <klebers@linux.vnet.ibm.com> Signed-off-by:
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- 12 Jul, 2012 1 commit
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Jia Hongtao authored
In SGMII riser card different PHY chip are used with different external IRQ from eTSEC. To support PHY link state auto detect in SGMII mode we should add another group of PHY nodes for SGMII mode. For MPC8572DS IRQ6 is used for PHY0~PHY1, IRQ7 is used for PHY2~PHY3. For MPC8544DS and MPC8536DS IRQ6 is used for PHY0~PHY1. For P2020DS IRQ5 is used for PHY1~PHY2. Signed-off-by:
Li Yang <leoli@freescale.com> Signed-off-by:
Jia Hongtao <B38951@freescale.com> Signed-off-by:
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- 11 Jul, 2012 20 commits
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Scott Wood authored
This gives the kernel a paravirtualized machine to target, without requiring both sides to pretend to be targeting a specific board that likely has little to do with the host in KVM scenarios. This avoids the need to add new boards to QEMU just to be able to run KVM on new CPUs. As this is the first platform that can run with either e500v2 or e500mc, CONFIG_PPC_E500MC is now a legitimately user configurable option, so add a help text. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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Scott Wood authored
Similar to how the primary PCI bridge is identified by looking for an isa subnode, we determine whether to apply uli exclusions by looking for a uli subnode. Signed-off-by:
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Scott Wood authored
As an alternative incremental starting point to Jia Hongtao's patchset, get the FSL PCI init out of the board files, but do not yet convert to a platform driver. Rather than having each board supply a magic register offset for determining the "primary" bus, we look for which PCI host bridge contains an ISA node within its subtree. If there is no ISA node, normally that would mean there is no primary bus, but until certain bugs are fixed we arbitrarily designate a primary in this case. Conversion to a platform driver and related improvements can happen after this, as the ordering issues are sorted out. Signed-off-by:
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Shengzhou Liu authored
Enable USB, MMC, SATA, LBC, MTD, NAND, SPI, PCIe, EDAC, VFAT, NFS, etc. Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by:
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Shengzhou Liu authored
- Enable NAND support - Enable CONFIG_PCI_MSI and CONFIG_MMC_SDHCI_OF Signed-off-by:
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Xu Jiucheng authored
The board is really P1021RDB-PC, so rename from p1021rdb.* to p1021rdb-pc.* Signed-off-by:
Xu Jiucheng <Jiucheng.Xu@freescale.com> Signed-off-by:
Matthew McClintock <msm@freescale.com> Signed-off-by:
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Shaohui Xie authored
Currently, BOOKE watchdog code for checking "wdt" and "wdt_period" is in setup_32.c, it cannot be used in 64-bit, so move it to a common place setup-common.c, which will be shared by 32-bit and 64-bit. Also, replace the simple_strtoul with kstrtol. Signed-off-by:
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Andreas Schwab authored
The i2c-powermac driver now creates the i2c devices properly from the device-tree, including workarounds for broken or missing device-tree bits, so let's just use the normal probe methods and get rid of the hand made device creation code. Signed-off-by:
Andreas Schwab <schwab@linux-m68k.org> Signed-off-by:
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Benjamin Herrenschmidt authored
This patch adds a number of workarounds for broken Apple device-trees mostly around sound chips. It handles creating the missing audio codec devices and works around various issues with missing addresses or missing compatible properties. Signed-off-by: -
Haren Myneni authored
Some power systems do not have legacy ISA devices. So, /dev/port is not a valid interface on these systems. User level tools such as kbdrate is trying to access the device using this interface which is causing the system crash. This patch will fix this issue by not creating this interface on these powerpc systems. Signed-off-by:
Haren Myneni <haren@us.ibm.com> Signed-off-by:
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Dong Aisheng authored
prom_update_property() currently fails if the property doesn't actually exist yet which isn't what we want. Change to add-or-update instead of update-only, then we can remove a lot duplicated lines. Suggested-by:
Grant Likely <grant.likely@secretlab.ca> Signed-off-by:
Dong Aisheng <dong.aisheng@linaro.org> Acked-by:
Rob Herring <rob.herring@calxeda.com> Signed-off-by:
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Tiejun Chen authored
Add "memory" attribute in inline assembly language as a compiler barrier to make sure 4.6.x GCC don't reorder mfmsr(). Signed-off-by:
Tiejun Chen <tiejun.chen@windriver.com> Signed-off-by:
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roger blofeld authored
Just like the module loader, ftrace needs to be updated to use r12 instead of r11 with newer gcc's. Signed-off-by:
Roger Blofeld <blofeldus@yahoo.com> Signed-off-by:
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Naveen N. Rao authored
If arch_validate_hwbkpt_settings() fails, bp->ctx won't be valid and the kernel panics. Add a check to fix this. Reported-by:
Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com> Signed-off-by:
Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by:
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Stephen Rothwell authored
This allows the linker to know that calls to them do not need to switch TOC and stop errors like the following when linking large configurations: powerpc64-linux-ld: drivers/built-in.o: In function `.gpiochip_is_requested': (.text+0x4): sibling call optimization to `_savegpr0_29' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `_savegpr0_29' extern Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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Anton Blanchard authored
We have a request for a fast method of getting CPU and NUMA node IDs from userspace. This patch implements a getcpu VDSO function, similar to x86. Ben suggested we use SPRG3 which is userspace readable. SPRG3 can be modified by a KVM guest, so we save the SPRG3 value in the paca and restore it when transitioning from the guest to the host. I have a glibc patch that implements sched_getcpu on top of this. Testing on a POWER7: baseline: 538 cycles vdso: 30 cycles Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
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Michael Ellerman authored
Purely for cosmetic purposes, otherwise it can appear that we are in single_step_pSeries() which is slightly confusing. Signed-off-by:
Michael Ellerman <michael@ellerman.id.au> Signed-off-by:
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Deepthi Dharwar authored
Currently the call to pseries_notify_cpuidle_add_cpu(), that takes action on the cpuidle front when a cpu is added/removed is being made from smp_xics_setup_cpu(). This caused lockdep issues as reported https://lkml.org/lkml/2012/5/17/2 On addition of each cpu, resources were cleared and re-allocated each time, all in critical section as part of start_secondary() call were interrupts are disabled. To resolve this issue, the pseries_notify_cpuidle_add_cpu() call is is being replaced by a hotplug notifier which would prevent cpuidle resources from being released and allocated each time cpu is onlined in the critical code path. It was fixed in https://lkml.org/lkml/2012/5/18/174. Also it is essential to call cpuidle_enable/disable_device between cpuidle_pause_and_lock() and cpuidle_resume_and_unlock() when used externally to avoid race conditions. Add support for CPU_ONLINE_FROZEN and CPU_DEAD_FROZEN as part of hotplug notify event for pseries_idle and unregister hotplug notifier while exiting out. The above mentioned issues are fixed as part of this patch. Signed-off-by:
Deepthi Dharwar <deepthi@linux.vnet.ibm.com> Signed-off-by:
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Benjamin Herrenschmidt authored
When I "fixed" the CONFIG_TRACE_IRQFLAGS case on interrupt entry, I screwed up a little bit with the test for user space vs. kernel. The code is fine, there's just some dead code around it. I basically removed the test and always create the added stack frame whether coming from user or kernel since in any case we do need to save a bunch of volatile registers or bad things would happen (we can take page faults in the kernel for example). Signed-off-by: -
Stuart Yoder authored
Signed-off-by:
Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by:
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- 10 Jul, 2012 9 commits
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Zhicheng Fan authored
Add device tree nodes to enable ucc uart support on P1025RDB. Signed-off-by:
Zhicheng Fan <B32736@freescale.com> Signed-off-by:
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Shawn Guo authored
Freescale PowerPC SoCs share a number of IP blocks with Freescale ARM/IMX SoCs, FlexCAN, SSI, FEC, eSDHC, USB, etc. There are some effort consolidating those drivers to make them work for both architectures. One outstanding difference between two architectures is ARM/IMX will turn off module clocks during platform initialization for power saving and expects drivers manage clocks using clk API, while PowerPC mostly does not do that, and thus does not always build in clk API. Listing all those driver Kconfig options in "select PPC_CLOCK if" seems not scalable for long term maintenance, and could easily introduce Kconfig recursive dependency. This patch chooses to select PPC_CLOCK unconditionally for FSL_SOC to always build clk API for PowerPC in. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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Kokoris, Ioannis authored
QE Microcode Initialization using qe_upload_microcode() does not work on P1021 if the IRAM-Ready register is not set after the microcode upload. Add a definition for the "I-RAM Ready" register and sets it upon microcode upload completion. Signed-off-by:
Ioannis Kokkoris <ioannis.kokoris@siemens-enterprise.com> Signed-off-by:
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Jia Hongtao authored
With 2-cell format interrupts of MSI PCIe ethernet card can not work. Signed-off-by:
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Jia Hongtao authored
The issue log on core1 is: root@mpc8572ds:~# ifconfig eth0 10.192.208.244 net eth0: could not attach to PHY SIOCSIFFLAGS: No such device To attach PHY node mdio@24520 should not be disabled in dts of core1. Because all PHYs are controlled through this node as follows: mdio@24520 { phy0: ethernet-phy@0 { interrupts = <10 1 0 0>; reg = <0x0>; }; phy1: ethernet-phy@1 { interrupts = <10 1 0 0>; reg = <0x1>; }; phy2: ethernet-phy@2 { interrupts = <10 1 0 0>; reg = <0x2>; }; phy3: ethernet-phy@3 { interrupts = <10 1 0 0>; reg = <0x3>; }; tbi0: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; Signed-off-by: -
Shaohui Xie authored
CONFIG_FSL_BOOKE is only defined in 32-bit, CONFIG_PPC_FSL_BOOK3E is defined in both 32-bit and 64-bit, so use CONFIG_PPC_FSL_BOOK3E to make driver work in 32-bit & 64-bit. Signed-off-by:
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Varun Sethi authored
We should use the MPIC_LARG_VECTORS flag while intializing the MPIC. This prevents us from eating in to hardware vector number space (MSIs) while setting up internal sources. Signed-off-by:
Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by:
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Liu Yu authored
So that we can call it when improving SPE switch like book3e did for fp switch. Signed-off-by:
Liu Yu <yu.liu@freescale.com> Signed-off-by:
Olivia Yin <hong-hua.yin@freescale.com> Signed-off-by:
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Prabhakar Kushwaha authored
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. The BSC9131 is integrated SoC that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. BSC9131RDB Overview ---------------------- BSC9131 SoC 1Gbyte DDR3 (on board DDR) 128Mbyte 2K page size NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory USB-ULPI eTSEC1: Connected to RGMII PHY eTSEC2: Connected to RGMII PHY DUART interface: supports one UARTs up to 115200 bps for console display Linux runs on e500v2 core and access some DSP peripherals like AIC Signed-off-by:Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by:
Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by:
Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by:
Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by:
Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by:
Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by:
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