- 26 Sep, 2017 40 commits
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Tony Cheng authored
need to program DCSURF_PRIMARY_SURFACE_ADDRESS last as HW automatically latch rest of addr regs on write when SURFACE_UPDATE_LOCK is not used Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Andrey Grodzovsky authored
You cannot have modeset and flip in the same call for same CRTC, in such case it will be set mode and set plane, not a flip. Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
Use DC interface to query for plane update type so in case of FULL update you flush any outstanding commits. Signed-off-by:
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Tom St Denis authored
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Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Tom St Denis authored
Also change sizeof to be automatic based on type declaration. Signed-off-by:
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
Simplify the function by removing identical looking code blocks. Signed-off-by:
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Ayyappa Chandolu authored
ASSR mode is not enable when we connect eDP panel via DP to eDP converter. connector_signal is coming as SIGNAL_TYPE_DISPLAY_PORT. Present code ignoring panel_mode_edp for SIGNAL_TYPE_DISPLAY_PORT. Added checking panel_mode_edp for all signals. Signed-off-by:
Ayyappa Chandolu <Ayyappa.Chandolu@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
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Leo (Sunpeng) Li authored
1. Implemented dcn10_ipp_program_input_lut(), following the existing interface. 2. Added missing registers as needed 3. Change to REG_GET for *ram_select() funcs. 4. Removed gamma table init from DiagsDM::make_surface() for resolving CRC errors. Reason: Legacy LUT will be deprecated soon for Raven in favor of degamma/regamma. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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Leo (Sunpeng) Li authored
use_lut() checks if the input surface's pixel format is compatible with a 256 entry LUT. This function can be used across different versions and not just dce11. Signed-off-by:
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Dmytro Laktyushkin authored
Apply dc_get_validate_context re-entrancy fix to dc_validate_resources instead Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Roman Li authored
- fixing bug in calculation of reg offset for D5VGA_CONTROL Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Tony Cheng authored
instead of GC, as after GFX off, GC can be power gated any time Signed-off-by:
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Andrey Grodzovsky authored
Remove extra loop we have for page flips and do flips in same loop we do for surface create/update. Add documentation for synchronization between commits on different crtcs. Rename function to have DM prefix. Signed-off-by:
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Dmytro Laktyushkin authored
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Leo (Sunpeng) Li authored
Calling dcn10_cursor_set_position() before dcn10_cursor_set_attributes() with invalid (0-value) attributes can cause the ASIC to hang. This fix checks that address.quadpart is non-zero within set_position before calling set_attributes. Signed-off-by:
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Andrey Grodzovsky authored
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Andrey Grodzovsky authored
Today we use special interface for flip because of fear of cuncurency issues over dc->current_ctx. This should be no longer an issue when flipping on multiple CRTCs concurently since for fast update (as flip is) no new context is created and the exsisitng is not destroyed. For full updates case when removing or adding streams on once CRTC while flipping on another Adding all current active CRTC's states to the atomic commit in amdgpu_dm_atomic_check will garntee that any such full update commit will wait for completion of any outstanding flip. Signed-off-by:
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Dmytro Laktyushkin authored
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Amy Zhang authored
- Add immediate ABM disable when eDP is disabled - Fix purple screen when ABM is mistakenly enabled on non eDP display Signed-off-by:
Amy Zhang <Amy.Zhang@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
Typo in expresion. Signed-off-by:
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Dmytro Laktyushkin authored
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Amy Zhang authored
- Add BT2020 color space in the set output csc default Signed-off-by:
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Harry Wentland authored
As pointed out by kbuild test robot and Julia Lawall. CC: Julia Lawall <julia.lawall@lip6.fr> CC: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Harry Wentland authored
We should also use it to determine pipe count. Signed-off-by:
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Amy Zhang authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Corbin McElhanney authored
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Corbin McElhanney <corbin.mcelhanney@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Charlene Liu authored
DPM0, FCLK=MCLK, single channel bandwidth = dual channel bandwidth for the rest of the DPM levels, single channel bandwidth = 1/2 dual channel bandwidth Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Harry Wentland authored
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Yongqiang Sun authored
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Dmytro Laktyushkin authored
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