- 19 Jan, 2023 15 commits
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Krzysztof Kozlowski authored
Bindings expect OPP tables to start with "opp-table". Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230109112221.102473-2-krzysztof.kozlowski@linaro.org
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Dmitry Baryshkov authored
Follow the schema change and rename mdp nodes to generic name 'display-controller'. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
Follow the schema change and rename mdss nodes to generic name 'display-subsystem'. Signed-off-by:
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Dmitry Baryshkov authored
Add SoC-specific compat string to the MDP5 device nodes to ease distinguishing between various platforms. Signed-off-by:
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Robert Marko authored
It seems that clock-output-names for the USB3 QMP PHY-s where set without actually checking what is the GCC clock driver expecting, so clock core could never actually find the parents for usb0_pipe_clk_src and usb1_pipe_clk_src clocks in the GCC driver. So, correct the names to be what the driver expects so that parenting works. Before: gcc_usb0_pipe_clk_src 0 0 0 125000000 0 0 50000 Y gcc_usb1_pipe_clk_src 0 0 0 125000000 0 0 50000 Y After: usb3phy_0_cc_pipe_clk 1 1 0 125000000 0 0 50000 Y usb0_pipe_clk_src 1 1 0 125000000 0 0 50000 Y gcc_usb0_pipe_clk 1 1 0 125000000 0 0 50000 Y usb3phy_1_cc_pipe_clk 1 1 0 125000000 0 0 50000 Y usb1_pipe_clk_src 1 1 0 125000000 0 0 50000 Y gcc_usb1_pipe_clk 1 1 0 125000000 0 0 50000 Y Fixes: 5e09bc51 ("arm64: dts: ipq8074: enable USB support") Signed-off-by:Robert Marko <robimarko@gmail.com> Reviewed-by:
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Siddharth Manthan authored
Galaxy Tab A 8.0 is a tablet, very similar to Tab A 9.7 with major differences being the display and touchscreen. Add it's devicetree reusing a common dtsi from gt510. Signed-off-by:
Siddharth Manthan <siddharth.manthan@gmail.com> [Squashed multiple commits] Reviewed-by:
Nikita Travkin <nikita@trvn.ru> Signed-off-by:
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Jasper Korten authored
The Galaxy Tab A 9.7 (2015) is a Snapdragon 410 based tablet. This commit introduces basic support for the tablet including the following features: - SDHCI (internal and external storage) - USB Device Mode - UART - Regulators - WCNSS (WiFi/BT) - GPIO keys - Fuel gauge - Touchscreen - Accelerometer Part of the DT is split out into a common dtsi since the tablet shares majority of the design with another variant having a different screen size. Signed-off-by:
Jasper Korten <jja2000@gmail.com> Co-developed-by:
Siddharth Manthan <siddharth_manthan@outlook.com> Signed-off-by:
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Brian Masney authored
Add the necessary device tree node for qcom,prng-ee so we can use the hardware random number generator. This functionality was tested on a SA8540p automotive development board using kcapi-rng from libkcapi. Signed-off-by:
Brian Masney <bmasney@redhat.com> Reviewed-by:
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Brian Masney authored
Add aliases for i2c4 and i2c21 to the crd and x13s DTS files so that what's exposed to userspace doesn't change in the future if additional i2c buses are enabled on these platforms. Signed-off-by:
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Brian Masney authored
Add the necessary nodes in order to get i2c0, i2c1, i2c12, i2c15, and i2c18 functioning on the automotive board and exposed to userspace. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. This change was validated by using i2c-tools 4.3.3 on CentOS Stream 9: [root@localhost ~]# i2cdetect -l i2c-0 i2c Geni-I2C I2C adapter i2c-1 i2c Geni-I2C I2C adapter i2c-12 i2c Geni-I2C I2C adapter i2c-15 i2c Geni-I2C I2C adapter i2c-18 i2c Geni-I2C I2C adapter [root@localhost ~]# i2cdetect -a -y 15 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: 70: Signed-off-by:Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by:
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Brian Masney authored
Add the missing nodes for the spi buses that's present on this SoC. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. Signed-off-by:
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Brian Masney authored
Add the missing nodes for the i2c buses that's present on this SoC. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. Signed-off-by:
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Brian Masney authored
In preparation for adding the missing SPI and I2C nodes to sc8280xp.dtsi, it was decided to rename all of the existing qupX_ uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead and rename qup0_i2c4 to i2c4. Note that some nodes are moved in the file by this patch to preserve the expected sort order in the file. Additionally, the properties within the pinctrl state node are sorted to match the expected order that's typically done in other DTs. Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Tested-by:
Steev Klimaszewski <steev@kali.org> Signed-off-by:
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Brian Masney authored
In preparation for adding the missing SPI and I2C nodes to sc8280xp.dtsi, it was decided to rename all of the existing qupX_ uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead and rename qup2_i2c5 to i2c21. Under the old name, this was the 5th index under qup2, which starts at index 16. Note that some nodes are moved in the file by this patch to preserve the expected sort order in the file. Additionally, the properties within the pinctrl state node are sorted to match the expected order that's typically done in other DTs. Signed-off-by:
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Brian Masney authored
In preparation for adding the missing SPI and I2C nodes to sc8280xp.dtsi, it was decided to rename all of the existing qupX_ uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead and rename qup2_uart17 to uart17. Note that some nodes are moved in the file by this patch to preserve the expected sort order in the file. Signed-off-by:
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- 18 Jan, 2023 25 commits
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Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
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Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
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Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
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Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
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Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
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Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
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Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
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Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
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Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
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Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
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Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
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Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
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Konrad Dybcio authored
One value escaped my previous lowercase hexification. Take care of it. Signed-off-by:
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Konrad Dybcio authored
Some lines were broken very aggresively, presumably to fit under 80 chars and some places could have used a newline, particularly between subsequent nodes. Address all that and remove redundant comments near PCIe ranges while at it so as not to exceed 100 chars needlessly. Signed-off-by:
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Konrad Dybcio authored
Order nodes by unit address if one exists and alphabetically otherwise. Signed-off-by:
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Konrad Dybcio authored
The dwc3 subnode was indented using spaces for some reason and other properties were not exactly properly indented. Fix it. Signed-off-by:
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Konrad Dybcio authored
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by:
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Abel Vesa authored
Enable PCIe controllers and PHYs nodes on SM8550 MTP board. Co-developed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Signed-off-by:
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Abel Vesa authored
Add PCIe controllers and PHY nodes. Signed-off-by:
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Neil Armstrong authored
Add the aDSP, cDSP and MPSS firmware and "Devicetree" firmware paths for the SM8550 MTP platform. Signed-off-by:
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Neil Armstrong authored
This adds support for the aDSP, cDSP and MPSS Subsystems found in the SM8550 SoC. The aDSP, cDSP and MPSS needs: - smp2p nodes to get event back from the subsystems - remoteproc nodes with glink-edge subnodes providing all needed resources to start and run the subsystems In addition, the MPSS Subsystem needs a rmtfs_mem dedicated memory zone. Signed-off-by:
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Abel Vesa authored
Add the interconnect path to SCM dts node. Signed-off-by:
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Neil Armstrong authored
Add nodes for the Visionox VTDR6130 found on the SM8550-MTP device. TLMM states are also added for the Panel reset GPIO and Tearing Effect signal for when the panel is running in DSI Command mode. Signed-off-by:
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Neil Armstrong authored
Enable MDSS/DPU/DSI0 on SM8550-MTP device. Signed-off-by:
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Neil Armstrong authored
Add devices tree nodes describing display hardware on SM8550: - Display Clock Controller - MDSS - MDP - two DSI controllers and DSI PHYs This does not provide support for DP controllers present on the SM8550. Reviewed-by:
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