- 05 Jul, 2022 36 commits
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Duncan Ma authored
[Why] Some panels may require more MST delay on discovery [How] Add panel patch and debug mst delay flag Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Duncan Ma <duncan.ma@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jimmy Kizito authored
[Why] Some TBT3 docks have DPOAs which report USB4 capability and are expected to support USB4 DPOA features such as FEC/DSC. [How] By default, do not override FEC/DSC capabilities reported by TBT3 docks. Reviewed-by:
Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com> Acked-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Tested-by:
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Rodrigo Siqueira authored
Recently we introduced a patch for fixing an MST issue, but it caused a regression on Club 3D since we could not set a refresh rate higher than 60Hz. This commit fixes this issue by adding a proper check after validating the stream. Fixes: f04d275d ("drm/amd/display: add mst port output bw check") Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Meenakshikumar Somasundaram authored
[Why] DC debug option to configure dpia hpd processing delay is not required. [How] Remove dc debug option for dpia hpd delay and also added log for querying dpia hpd state. Reviewed-by:
Mustapha Ghaddar <Mustapha.Ghaddar@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Chris Park authored
[Why] With ODM policy 2 to 1, there exists a new use case scenario where stream content is unchanged, but ODM may be used. When this happens, the stream needs to be committed with a new pipe setting. This did not happen due to stream change detection logic not accounting for ODM. [How] Set ODM flag in stream and commit stream when change in ODM has been detected due to policy change. Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Acked-by:
Chris Park <chris.park@amd.com> Tested-by:
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Dmytro Laktyushkin authored
This w/a has a bad interaction with seamless boot toggling an active stream. Most panels recover, however some fail leading to display corruption. Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by:
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Fangzhi Zuo authored
[Why] Unexpected change of aux hw mapping causes dmub soft hang when initiate aux transation at wrong aux channel. ddc_channel stands for hw dp aux index which is from vbios, but link_index is pure software concept for link count depending on which link is probed first. They are not interchangeable. dmub aux transaction could pass if happens eDP link_index gets the same value as vbios ddc_channel, e.g., ddc_channel = 1, link_index = 1 if they gets different, e.g., ddc_channel = 2, link_index = 0, overwrite ddc_channel with link_index will have wrong ddc channel being used for aux transaction in dmub PSR, cause aux transaction soft hang. [How] ddc_channel mapping to each link is determined by vbios and further parsed in dc. Such info. should not be touched in any kind, otherwise the mapping is screwed up leading to aux transaction timeout. Reviewed-by:
Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com> Acked-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why & How] Check lenc is not NULL since dynamic link encoder assignment could end up assigning a NULL link encoder. Reviewed-by:
Michael Strauss <Michael.Strauss@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] It's possible that we don't have a link encoder assignment if the context is NULL but we're calling dc_add_stream_to_ctx from DM directly. Link encoder assignment will happen later after global validation runs with fast_validate = false. [How] Remove the ASSERTION. We already guard against NULL link_enc. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] In the case where we don't support DMUB aux but we have DPIA links in the configuration we might try to message AUX using the legacy path - where DDC pin is NULL. This causes a NULL pointer dereference. [How] Guard against NULL DDC pin, return a failure for aux engine acquire. Reviewed-by:
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Alan Liu authored
- Setup the shift and mask of HDMI_ACP_SEND register - Program the register in hdmi stream encoder - Also update ACP register in azalia configuration Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
Alan Liu <HaoPing.Liu@amd.com> Tested-by:
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Evgenii Krasnikov authored
[HOW/WHY] Add an option to skip edp_wait_for_hpd_ready when necessary Reviewed-by:
Jayendran Ramani <Jayendran.Ramani@amd.com> Acked-by:
Evgenii Krasnikov <Evgenii.Krasnikov@amd.com> Tested-by:
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Alvin Lee authored
[Description] In general cases we want to keep the dram clock change requirement (we prefer configs that support MCLK switch). Only override to false for SubVP. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Jun Lei authored
[why] Some parts are consuming dangerously close to maximum number of states supported when updating the BB (i.e. 8). [how] Change maximum stages from 9 to 20. Acked-by:
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Jimmy Kizito authored
[Why] While applying a state to hardware, there is a transition period where the back-end is reset using the old state; then enabled using the new state. Generally, the link encoder configuration module queries stream-to-encoder assignments in either the new or old state based on a mode variable. During the transition there is a need to query both states, however toggling this mode variable can lead to incorrect programming of encoders. [How] - Add new function to explicity query stream-to-encoder assignment in the current state rather than intermittently switch the mode of operation of the link encoder assignment module. - Add additional checks for encoder assignment defects. - Explicitly reset the mode of operation if application of state to hardware ends prematurely. Acked-by:
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Martin Leung authored
[Why]: On power down, virtual dal may try to delete link_encoders by referencing uninitialized res_pool. [How]: Added guard against empty res_pool. Acked-by:
Martin Leung <martin.leung@amd.com> Tested-by:
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Dmytro Laktyushkin authored
Fix for a bug where we would try to timing sync 2 odm halves. Acked-by:
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Rodrigo Siqueira authored
[WHY?] When adding/removing a plane to some configurations, unsupported pipe programming can occur when moving to a new plane. Such cases include pipe split on multi-display, with MPO, and/or ODM. [HOW?] Add a safe transistion state that minimizes pipe usage before programming new configuration. When adding a plane, the current state has the least pipes required so it is applied without splitting. This must be applied prior to updating the plane_state for seamless transition. When removing a plane, the new state has the least pieps required so it is applied without splitting. Signed-off-by:
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Rodrigo Siqueira authored
Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Found when running igt@kms_atomic. Userspace attempts to do a TEST_COMMIT when 0 streams which calls dc_remove_stream_from_ctx. This in turn calls link_enc_unassign which ends up modifying stream->link = NULL directly, causing the global link_enc to be removed preventing further link activity and future link validation from passing. [How] We take care of link_enc unassignment at the start of link_enc_cfg_link_encs_assign so this call is no longer necessary. Fixes global state from being modified while unlocked. Signed-off-by:
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Rodrigo Siqueira authored
We want to enable Firmware Assisted Memory (FAMS) Switching, but first, we need to add the required code infrastructure in DC before allowing it in amdgpu_dm. Signed-off-by:
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Alvin Lee authored
[Why] Newer DCN should use optc3 [How] Declare optc3 vmin/vmax function in header. Signed-off-by:
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Eric Bernstein authored
After some experimental tests, we noticed that we need to set gpuvm_max_page_table_levels to '4' to meet the hardware requirements. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Tested-by:
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Chris Park authored
[Why] For Pixel Rate control, when on HDMI, HDMI DTO should be selected instead of DP DTO. [How] Pass HDMI parameter for HDMI stream, and select correct DTO. Signed-off-by:
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Alvin Lee authored
For MPO we want to allocate less than maximum DET for MPO pipes because we need enogh buffer to move DET back to other pipes when removing an MPO plane. Also update regular DET allocation to use DET override (DCN32 has an internal policy which driver does not want to use) Signed-off-by:
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Rodrigo Siqueira authored
Currently, we check if pixel_encoding is equal to PIXEL_ENCODING_YCBCR422 to get the k1/k2 div parameters. This commit changes this logic slightly by checking if two pixels per container are used. Signed-off-by:
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Samson Tam authored
[Why] Most of the time, a single display uses the ODM combine. When using multi-display, we use ODM combine only if it is necessary. These cases are not flexible enough for us, and we can improve them to take advantage of our hardware. We want to have more control over the ODM policy. [How] This commit add a new debug flag named enable_single_display_2to1_odm_policy to control the ODM policy and another flag named enable_dp_dig_pixel_rate_div_policy to fine control the ODM combine. This is possible by adding a new "pipe.dest" parameter that can be set to ODM 2:1 combined if we use a single display. For dynamic ODM combine, when using DP-DIG, DCN applies K2=2 settings for ODM combine. Note that this feature affects the following registers: - timing.pix_clk_100khz -> DP_VID_M, DP_VID_N - requested_pix_clk_100hz -> DP_DTOn_PHASE - OTGn_PIXEL_RATE_DIVK2 - DP_PIXEL_PER_CYCLE_PROCESSING_MODE - DIG_FIFO_OUTPUT_PIXEL_MODE - DP_VID_N_MUL Acked-by:
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Eric Bernstein authored
Add function to set pixels per cycle in DIG stream encoder Acked-by:
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Martin Leung authored
[WHY]: Lut pipeline will be hooked up differently in some asics need to add new interfaces and missing registers. [HOW]: Add missing registers and hook up programming from DPP for pre-blend lut. Acked-by:
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Alvin Lee authored
This commit enables the SubVP feature. To achieve that, we need to: - Don't force p-state disallow on SubVP (can't block dummy p-state) - Send calculated watermark to DMCUB for SubVP - Adjust CAB mode message to PMFW - Add a proper locking sequence for SubVP - Various fixes to SubVP static analysis and determining SubVP config - Currently SubVP not supported with pipe split so merge all pipes before setting up SubVp Reviewed-by:
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Rodrigo Siqueira authored
We are missing some ACP registers/mask value for some specific ASICs. This commit includes it to those ASICs that support it. Signed-off-by:
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Stanley.Yang authored
It should not init whole ras bad page framework on sriov guest side due to it is handled on host side. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Stanley.Yang authored
GFX is the only IP block that RAS TA needs to program the hardware when receiving enable_feature command. Changed from V1: remove amdgpu_ras_need_send_ras_feature inline function, use GFX RAS block check directly. Signed-off-by: -
Evan Quan authored
And bump the version to 0x2A. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Lang Yu authored
We don't need to validate and map root PD specially here, it would be validated and mapped by amdgpu_vm_validate_pt_bos if it is evicted. The special case is when turning a GFX VM to a compute VM, if vm_update_mode changed, we should make sure root PD gets mapped. So just map root PD after updating vm->update_funcs in amdgpu_vm_make_compute whether the vm_update_mode changed or not. v3: - Add some comments suggested by Christian. v2: - Don't rename vm_validate_pt_pd_bos and make it public. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Expose a new dc debug mask enum to force a subviewport memory clock switch to facilitate easy testing. Signed-off-by:
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- 30 Jun, 2022 4 commits
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Alex Deucher authored
Properly handle FP code in dcn32_clk_mgr.c. Fixes: 265280b9 ("drm/amd/display: add CLKMGR changes for DCN32/321") Reviewed-by:
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Rodrigo Siqueira authored
When we tried to compile DCN32/321 for 32-bit architecture, we got this error message: ERROR: modpost: "__nedf2" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! This commit fixes this issue by rewriting a small part of the dcn32_build_wm_range_table. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Randy Dunlap <rdunlap@infradead.org> Fixes: 265280b9 ("drm/amd/display: add CLKMGR changes for DCN32/321") Acked-by:
Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Reviewed-by:
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Rodrigo Siqueira authored
Sometimes when trying to enable some feature, we have to define some values with educated guesses, but we mark those values as TBD, which means "To Be Determined". However, the correct way to approach it is by loading that information from the firmware. Anyway, some of the values that we were experimenting with caused this issue: ERROR: modpost: "__muldf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! This commit fixes this issue by removing the division by two since it is harmless in this case. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Randy Dunlap <rdunlap@infradead.org> Fixes: 265280b9 ("drm/amd/display: add CLKMGR changes for DCN32/321") Acked-by:
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Rodrigo Siqueira authored
When we tried to compile DCN32/321 for 32-bit architecture, we got this error message: ERROR: modpost: "__floatunsidf" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! This was caused because we were trying to assign an unsigned int to a double value which causes issues for 32-bit architecture. This issue can be fixed by changing the value type. Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Randy Dunlap <rdunlap@infradead.org> Fixes: 265280b9 ("drm/amd/display: add CLKMGR changes for DCN32/321") Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Acked-by:
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