- 10 Sep, 2009 40 commits
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Andre Przywara authored
Handle #UD intercept of the sysenter instruction in 32bit compat mode on an AMD host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Signed-off-by:
Christoph Egger <christoph.egger@amd.com> Signed-off-by:
Amit Shah <amit.shah@redhat.com> Signed-off-by:
Andre Przywara <andre.przywara@amd.com> Signed-off-by:
Avi Kivity <avi@redhat.com>
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Andre Przywara authored
Handle #UD intercept of the syscall instruction in 32bit compat mode on an Intel host. Setup the segment descriptors for CS and SS and the EIP/ESP registers according to the manual. Save the RIP and EFLAGS to the correct registers. [avi: fix build on i386 due to missing R11] Signed-off-by:
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Andre Przywara authored
Add the flags needed for syscall, sysenter and sysexit to the opcode table. Catch (but for now ignore) the opcodes in the emulation switch/case. Signed-off-by:
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Andre Przywara authored
Signed-off-by:
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Andre Przywara authored
Add the opcodes for syscall, sysenter and sysexit to the list of instructions handled by the undefined opcode handler. Signed-off-by:
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Marcelo Tosatti authored
This allows use of the powerful ftrace infrastructure. See Documentation/trace/ for usage information. [avi, stephen: various build fixes] [sheng: fix control register breakage] Signed-off-by:
Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
Sheng Yang <sheng@linux.intel.com> Signed-off-by:
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Alexander Graf authored
While trying to get Hyper-V running, I realized that the interrupt injection mechanisms that are in place right now are not 100% correct. This patch makes nested SVM's interrupt injection behave more like on a real machine. Signed-off-by:
Alexander Graf <agraf@suse.de> Signed-off-by:
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Alexander Graf authored
SVM adds another way to do INVLPG by ASID which Hyper-V makes use of, so let's implement it! For now we just do the same thing invlpg does, as asid switching means we flush the mmu anyways. That might change one day though. Signed-off-by:
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Alexander Graf authored
Hyper-V uses some MSRs, some of which are actually reserved for BIOS usage. But let's be nice today and have it its way, because otherwise it fails terribly. [jaswinder: fix build for linux-next changes] Signed-off-by:
Jaswinder Singh Rajput <jaswinderrajput@gmail.com> Signed-off-by:
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Alexander Graf authored
Hyper-V accesses MSR_IGNNE while running under KVM. Signed-off-by:
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Avi Kivity authored
The host never reads cr2 in process context, so are free to clobber it. The vmx code does this, so we can safely remove the save/restore code. Signed-off-by: -
Avi Kivity authored
cr2 changes only rarely, and writing it is expensive. Avoid the costly cr2 writes by checking if it does not already hold the desired value. Shaves 70 cycles off the vmexit latency. Signed-off-by: -
Jan Kiszka authored
The current code tries to optimize the setting of KVM_REQ_PENDING_TIMER but used atomic_inc_and_test - which always returns true unless pending had the invalid value of -1 on entry. This patch drops the test part preserving the original semantic but expressing it less confusingly. Signed-off-by:
Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by:
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Jan Kiszka authored
Minor issue that likely had no practical relevance: the kvm timer function so far incremented the pending counter and then may reset it again to 1 in case reinjection was disabled. This opened a small racy window with the corresponding VCPU loop that may have happened to run on another (real) CPU and already consumed the value. Fix it by skipping the incrementation in case pending is already > 0. This opens a different race windows, but may only rarely cause lost events in case we do not care about them anyway (!reinject). Signed-off-by:
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Gleb Natapov authored
Most of the time IRR is empty, so instead of scanning the whole IRR on each VM entry keep a variable that tells us if IRR is not empty. IRR will have to be scanned twice on each IRQ delivery, but this is much more rare than VM entry. Signed-off-by:
Gleb Natapov <gleb@redhat.com> Signed-off-by:
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Gleb Natapov authored
Replace previous exception with a new one in a hope that instruction re-execution will regenerate lost exception. Signed-off-by:
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Marcelo Tosatti authored
Disable usage of 2M pages if VMX_EPT_2MB_PAGE_BIT (bit 16) is clear in MSR_IA32_VMX_EPT_VPID_CAP and EPT is enabled. [avi: s/largepages_disabled/largepages_enabled/ to avoid negative logic] Signed-off-by:
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Marcelo Tosatti authored
Handler for EPT misconfiguration which checks for valid state in the shadow pagetables, printing the spte on each level. The separate WARN_ONs are useful for kerneloops.org. Signed-off-by:
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Marcelo Tosatti authored
Required by EPT misconfiguration handler. Signed-off-by:
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Marcelo Tosatti authored
This way there is no need to add explicit checks in every for_each_shadow_entry user. Signed-off-by:
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Marcelo Tosatti authored
Required for EPT misconfiguration handler. Signed-off-by:
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Andre Przywara authored
The performance counter MSRs are different for AMD and Intel CPUs and they are chosen mainly by the CPUID vendor string. This patch catches writes to all addresses (regardless of VMX/SVM path) and handles them in the generic MSR handler routine. Writing a 0 into the event select register is something we perfectly emulate ;-), so don't print out a warning to dmesg in this case. This fixes booting a 64bit Windows guest with an AMD CPUID on an Intel host. Signed-off-by:
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Marcelo Tosatti authored
Make the audit code aware of largepages. Signed-off-by:
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Marcelo Tosatti authored
- Fail early in case gfn_to_pfn returns is_error_pfn. - For the pre pte write case, avoid spurious "gva is valid but spte is notrap" messages (the emulation code does the guest write first, so this particular case is OK). Signed-off-by:
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Marcelo Tosatti authored
It is valid to set non leaf sptes as notrap. Signed-off-by:
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Marcelo Tosatti authored
- Unsync pages contain writable sptes in the rmap. - rmaps do not exclusively contain writable sptes anymore. Signed-off-by:
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Marcelo Tosatti authored
Under testing, count_writable_mappings returns a value that is 2 integers larger than what count_rmaps returns. Suspicion is that either of the two functions is counting a duplicate (either positively or negatively). Modifying check_writable_mappings_rmap to check for rmap existance on all present MMU pages fails to trigger an error, which should keep Avi happy. Also introduce mmu_spte_walk to invoke a callback on all present sptes visible to the current vcpu, might be useful in the future. Signed-off-by:
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Marcelo Tosatti authored
Hiding some of the last largepage / level interaction (which is useful for gbpages and for zero based levels). Also merge the PT_PAGE_TABLE_LEVEL clearing loop in unlink_children. Signed-off-by:
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Avi Kivity authored
Instead of mindlessly retrying to execute the instruction, report the failure to userspace. Signed-off-by: -
Gleb Natapov authored
[christian: remove unused variables on s390] Signed-off-by:
Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by:
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Gleb Natapov authored
Archs are free to use vcpu_id as they see fit. For x86 it is used as vcpu's apic id. New ioctl is added to configure boot vcpu id that was assumed to be 0 till now. Signed-off-by:
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Gleb Natapov authored
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Gleb Natapov authored
Use it instead of open code "vcpu_id zero is BSP" assumption. Signed-off-by:
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Avi Kivity authored
We use shadow_pte and spte inconsistently, switch to the shorter spelling. Rename set_shadow_pte() to __set_spte() to avoid a conflict with the existing set_spte(), and to indicate its lowlevelness. Signed-off-by: -
Avi Kivity authored
Since the guest and host ptes can have wildly different format, adjust the pte accessor names to indicate on which type of pte they operate on. No functional changes. Signed-off-by: -
Avi Kivity authored
is_dirty_pte() is used on guest ptes, not shadow ptes, so it needs to avoid shadow_dirty_mask and use PT_DIRTY_MASK instead. Misdetecting dirty pages could lead to unnecessarily setting the dirty bit under EPT. Signed-off-by: -
Avi Kivity authored
rmode is only used in vmx, so move it to vmx.c Signed-off-by: -
Avi Kivity authored
Somehow the VM ioctls got unsorted; resort. Signed-off-by: -
Nitin A Kamble authored
"Unrestricted Guest" feature is added in the VMX specification. Intel Westmere and onwards processors will support this feature. It allows kvm guests to run real mode and unpaged mode code natively in the VMX mode when EPT is turned on. With the unrestricted guest there is no need to emulate the guest real mode code in the vm86 container or in the emulator. Also the guest big real mode code works like native. The attached patch enhances KVM to use the unrestricted guest feature if available on the processor. It also adds a new kernel/module parameter to disable the unrestricted guest feature at the boot time. Signed-off-by:Nitin A Kamble <nitin.a.kamble@intel.com> Signed-off-by:
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Marcelo Tosatti authored
Protect irq injection/acking data structures with a separate irq_lock mutex. This fixes the following deadlock: CPU A CPU B kvm_vm_ioctl_deassign_dev_irq() mutex_lock(&kvm->lock); worker_thread() -> kvm_deassign_irq() -> kvm_assigned_dev_interrupt_work_handler() -> deassign_host_irq() mutex_lock(&kvm->lock); -> cancel_work_sync() [blocked] [gleb: fix ia64 path] Reported-by:Alex Williamson <alex.williamson@hp.com> Signed-off-by:
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