- 20 Sep, 2023 40 commits
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Vignesh Chander authored
Host handles PG. Signed-off-by:
Vignesh Chander <Vignesh.Chander@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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YuBiao Wang authored
Directly use tbo's start address will miss the domain start offset. Need to use gpu_offset instead. Signed-off-by:
YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Aric Cyr authored
Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Anthony Koo authored
- Add new IPS ALLOW masks - Add new Replay power configuration options Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Acked-by:
Anthony Koo <anthony.koo@amd.com> Signed-off-by:
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Muhammad Ahmed authored
MST now recognizes both connected displays Tested-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Signed-off-by:
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Charlene Liu authored
Fix some non-initialized register mask and update golden setting. Tested-by:
Duncan Ma <duncan.ma@amd.com> Acked-by:
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Roman Li authored
Enable the display replay feature for DCN35. Tested-by:
Roman Li <roman.li@amd.com> Signed-off-by:
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Gabe Teeger authored
Add a config option to disable odm dispclk optimization for debug purpose. Tested-by:
Gabe Teeger <gabe.teeger@amd.com> Signed-off-by:
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Muhammad Ahmed authored
Disable IPS by default till it is ready. Tested-by:
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Sung Joon Kim authored
[why] Currently, driver is not aware if IPS is supported. After PMFW helps implement new message query functionality, driver will set IPS capability flag. [how] Create new SMU hook function to query IPS capability. Based on the cap, set appropriate flags to false for power-gating purposes. This will avoid keeping SMU busy and offloading tasks to DMUB/driver. Tested-by:
Sung Joon Kim <sungkim@amd.com> Signed-off-by:
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Duncan Ma authored
[Why] Two issues fixed: 1. Currently, driver does not allow idle prior to PSR entry. Once PSR1+IPS is enabled, there is intermittent hang due to DCN access from IrqMgr during IPS2. 2. Driver is sending multiple commands to PMFW and dmcub to exit IPS even during IPS0. [How] 1. Set driver allow optimization prior to entering PSR mode with the condition for eDP display only. Unregister all interrupts before allowing driver idle and re-register interrupts when exiting from idle. This will prevent IrqMgr to access DCN during IPS2. 2. Block sending PMFW and dmcub exit low power state commands when driver is not in idle state. Tested-by:
Jun Lei <jun.lei@amd.com> Reviewed-by:
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Charlene Liu authored
Correct z8_watermark mask from 16bit to 20bit. Also, do not set dcn35 dprefclk in clk_mgr_construct. Tested-by:
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Artem Grishin authored
[Why] The STREAM_MAPPER_CONTROL register offset was left uninitialized, causing warning in the driver log at runtime [How] A temporary solution to add it into dcn35_create_resource_pool. [TODO] Remove duplication between SE_DCN35_REG_LIST_RI in dcn35_resource.h and SE_DCN35_REG_LIST in dcn35_dio_stream_encoder.h Tested-by:
Artem Grishin <artem.grishin@amd.com> Signed-off-by:
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Wenjing Liu authored
Pipe resource interfaces were changed. Tested-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Mustapha Ghaddar authored
For DPIA we should have preferred DIG assignment based on DPIA selected as per the ASIC design Tested-by:
George Shen <george.shen@amd.com> Acked-by:
Mustapha Ghaddar <mghaddar@amd.com> Signed-off-by:
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Sung-huai Wang authored
set_static_screen_control has been updated for DCN3 series. Update it for DCN35. Tested-by:
Sung-huai Wang <danny.wang@amd.com> Signed-off-by:
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Sung Joon Kim authored
Call to immediate_disable_crtc was not checked before calling, exposing a potential null pointer hang. Tested-by:
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Muhammad Ahmed authored
PMFW ungate this feature, this can be enabled now Tested-by:
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Qingqing Zhuo authored
Add DCN 35 case for dc_clk_mgr_create. Tested-by:
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Charlene Liu authored
Add z8 watermarks to struct for DCN35. Tested-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
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Duncan Ma authored
[Why] Some of the stream encoder registers have register offset address 0. It is causing no display in some scenarios due to DIG_FE was not setup correctly and was not enabled. [How] Fix stream encoder register define list. Tested-by:
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Hamza Mahfooz authored
On eDP we can receive invalid modes from dm_update_crtc_state() for entirely new streams for which drm_mode_set_crtcinfo() shouldn't be called on. So, instead of calling drm_mode_set_crtcinfo() from within create_stream_for_sink() we can instead call it from amdgpu_dm_connector_mode_valid(). Since, we are guaranteed to only call drm_mode_set_crtcinfo() for valid modes from that function (invalid modes are rejected by that callback) and that is the only user of create_validate_stream_for_sink() that we need to call drm_mode_set_crtcinfo() for (as before commit cb841d27 ("drm/amd/display: Always pass connector_state to stream validation"), that is the only place where create_validate_stream_for_sink()'s dm_state was NULL). Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2693 Fixes: cb841d27 ("drm/amd/display: Always pass connector_state to stream validation") Tested-by:
Mark Broadworth <mark.broadworth@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Charlene Liu authored
Temporarily disable dchubbub clock gating, registers: .DISPCLK_R_DCHUBBUB_GATE_DIS .DCFCLK_R_DCHUBBUB_GATE_DIS need to follow up with sequence issue. Tested-by:
Leo Chen <sanchuan.chen@amd.com> Acked-by:
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Muhammad Ahmed authored
Disable clock gating logic. Tested-by:
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Taimur Hassan authored
To prevent confusion after symclk has already been disabled. Tested-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Acked-by:
Taimur Hassan <syed.hassan@amd.com> Signed-off-by:
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André Almeida authored
Instead of storing coredump information inside amdgpu_device struct, move if to a proper separated struct and allocate it dynamically. This will make it easier to further expand the logged information. Signed-off-by:
André Almeida <andrealmeid@igalia.com> Reviewed-by:
Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
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Joshua Ashton authored
This was never filled in and thus never truly used. Checking the EDID for content_type support is not required for sending the avi infoframe packet. v2: - rebase to amd-staging-drm-next Reviewed-by:
Melissa Wen <mwen@igalia.com> Reviewed-by:
Joshua Ashton <joshua@froggi.es> Signed-off-by:
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Joshua Ashton authored
Implements the 'content type' property for HDMI connectors. Verified by checking the avi infoframe on a connected TV. This also simplifies a lot of the code in that area as well, there were a lot of temp variables doing very little and unnecessary logic that was quite confusing. It is not necessary to check for support in the EDID before sending a 'content type' value in the avi infoframe also. v2: - rebase to amd-staging-drm-next - mark CRTC state for reset if content_type differs Reviewed-by: Harry Wentland <harry.wentland@amd.com> (v1) Signed-off-by:
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Cong Liu authored
This patch fixes a memory leak in the amdgpu_ras_feature_enable() function. The leak occurs when the function sends a command to the firmware to enable or disable a RAS feature for a GFX block. If the command fails, the kfree() function is not called to free the info memory. Fixes: 9f051d6f ("drm/amdgpu: Free ras cmd input buffer properly") Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Cong Liu <liucong2@kylinos.cn> Signed-off-by:
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Lijo Lazar authored
Search for vbios version string in STRING_OFFSET-ATOM_ROM_HEADER region first. If those offsets are not populated, use the hardcoded region. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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Lijo Lazar authored
This reverts commit 7748ce5b. vbios_version sysfs node is used to identify Part Number also. Revert to the same so that it doesn't break scripts/software which parse this. Signed-off-by:
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Yang Wang authored
v1: implement smu_v13_0_6 mca bank interface. v2: - remove unnecessary lock - move MCMP1_* macros to mp_13_0_6_sh_mask.h file Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
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Yang Wang authored
update smu header to support mca dump interface. Signed-off-by:
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David Francis authored
These flags (for GEM and SVM allocations) allocate memory that allows for system-scope atomic semantics. On GFX943 these flags cause caches to be avoided on non-local memory. On all other ASICs they are identical in functionality to the equivalent COHERENT flags. Corresponding Thunk patch is at https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/pull/88Reviewed-by:
David Yat Sin <David.YatSin@amd.com> Signed-off-by:
David Francis <David.Francis@amd.com> Signed-off-by:
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Jonathan Kim authored
There are cases where HSA runtime is not enabled through the AMDKFD_IOC_RUNTIME_ENABLE call when adding queues and the MES ADD_QUEUE API should clear the MES process context instead of SET_SHADER_DEBUGGER. Such examples are legacy HSA runtime builds that do not support the current exception handling and running KFD tests. The only time ADD_QUEUE.skip_process_ctx_clear is required is for debugger use cases where a debugged process is always runtime enabled when adding a queue. Tested-by:
Shikai Guo <shikai.guo@amd.com> Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Acked-by:
Felix Kuehling <felix.kuehling@amd.com> Reviewed-by:
Eric Huang <jinhuieric.huang@amd.com> Signed-off-by:
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Yang Wang authored
add amdgpu mca debug sysfs support. Signed-off-by:
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Alex Deucher authored
Add missing IP discovery info. Reviewed-by:
Lang Yu <lang.yu@amd.com> Signed-off-by:
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Yang Wang authored
add amdgpu smu mca dump feature support. Signed-off-by:
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Lijo Lazar authored
pp_dpm_*clk nodes also could show the frequencies when a clock is in 'sleep' state. Add documentation related to that. Signed-off-by:
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Mario Limonciello authored
Seamless boot can technically be supported as far back as DCN1 but to avoid regressions on older hardware, enable it for DCN3 and later. If users report using the module parameter that it works on older ASICs as well, this can be adjusted. Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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