- 06 Oct, 2021 29 commits
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Jimmy Kizito authored
[Why] DIB_BE_CNTL<i>.DIG_HPD_SELECT selects the HPD block being used by the display endpoint assigned to DIG<i>. In the case of USB4 display endpoints, no physical HPD block is assigned. [How] Setting DIB_BE_CNTL<i>.DIG_HPD_SELECT to 5 indicates that no HPD is assigned to a display endpoint. Firmware decrements the HPD_SELECT value by 1 before writing it to the register. Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Acked-by:
Wayne Lin <Wayne.Lin@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jude Shih authored
[Why] To process SET_CONFIG transactions with DMUB using inbox1 and outbox1 mail boxes. [How] 1) DMUB posts SET_CONFIG reply as an Outbox1 message of type DMUB_OUT_CMD__SET_CONFIG_REPLY. 2) The dmub async to sync mechanism for AUX is modified to accommodate SET_CONFIG commands for both command issue and reply code paths. Reviewed-by:
Jude Shih <shenshih@amd.com> Signed-off-by:
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Meenakshikumar Somasundaram authored
[Why & How] To add support for dpia debug options. Reviewed-by:
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Jimmy Kizito authored
[Why] We requires information from DPCD in order to identify USB4 DP tunneling targets. [How] Add USB4 DP tunneling fields to DPCD struct and populate these fields during sink detection. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Meenakshikumar Somasundaram authored
[Why] To process SET_CONFIG transactions with DMUB using inbox1 and outbox1 mail boxes. [How] 1) Added inbox1 DPIA command subtype DMUB_CMD__DPIA_SET_CONFIG_ACCESS to issue SET_CONFIG command to DMUB in dc_process_dmub_set_config_async(). DMUB processes the command with DPIA sends reply back immediately or in an outbox1 message triggering an outbox1 interrupt to driver. 2) DMUB posts SET_CONFIG reply as an Outbox1 message of type DMUB_OUT_CMD__SET_CONFIG_REPLY. 3) The dmub async to sync mechanism for AUX is modified to accommodate SET_CONFIG commands for both command issue and reply code paths. Reviewed-by:
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Jimmy Kizito authored
[Why & How] Clear training pattern sequence for hop in display path once clock recovery and equalization phases of DP tunnel link training completed. Reviewed-by:
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Jimmy Kizito authored
[Why] Equalisation is the mandatory second phase of DisplayPort link training over a USB4 DP tunnel. [How] Implement equalisation phase for DP tunneled over USB4 in DPIA training module. Reviewed-by:
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Jimmy Kizito authored
[Why] Clock recovery is the mandatory first phase of DP link training. [How] - Implement clock recovery phase in DPIA training module. - Add helper functions for building SET_CONFIG messages. Reviewed-by:
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Jimmy Kizito authored
[Why] Training settings need to be applied to DPIA link at start of each training loop. Note: FEC readiness should be configured before link training while FEC enablement should be configured once training is complete. [How] - Implement DPIA link configuration function. - Account for dynamically assigned link encoders during link configuration. Reviewed-by:
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Jimmy Kizito authored
[Why] Training of DPIA link differs enough from that of conventional DP link to warrant a separate implementation. [How] - Implement top-level of DPIA training loop. - Make functions shared between DP and DPIA link training "public". Reviewed-by:
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Jimmy Kizito authored
[Why & How] Conventional links are trained with fallback during sink detection. Have DPIA links trained with fallback too. Reviewed-by:
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Jimmy Kizito authored
[why & how] Driver does not need to train the first hop. Reviewed-by:
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Jimmy Kizito authored
[why & how] 1. Add stub for getting tunneling device data 2. Add check for phy_repeater_cnt < 0xff to LTTPR check 3. Add two more bits of information to DPIA links Reviewed-by:
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Jimmy Kizito authored
[why & how] Add stub for DPIA link training and define new DPIA DMUB commands to support it. Reviewed-by:
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Jimmy Kizito authored
[why & how] We will need a way to distinguish physically connected links and DPIA endpoints. Reviewed-by:
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Meenakshikumar Somasundaram authored
[WHY] To add support for HPD & HPD RX interrupt handling for USB4 DPIA in YELLOW_CARP_B0. USB4 DPIA HPD & HPD RX interrupts are issued from DMUB to driver as a outbox1 message. [HOW] 1) Created get_link_index_from_dpia_port_index() to retrieve link index from dpia port index for HPD & HPD RX dmub notifications. 2) Added DMUB HPD & HPD RX handling in dmub_srv_stat_get_notification(). Reviewed-by:
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Meenakshikumar Somasundaram authored
[WHY] To enable dc links for USB4 DPIA ports and AUX command tunneling for YELLOW_CARP_B0. [HOW] 1) Created dc links for all USB4 DPIA ports in create_links(). dc_link_construct() implementation is split for legacy DDC and DPIAs. As usb4 has no ddc, ddc->ddc_pin will be set to NULL for its dc link and this parameter will be used to identify the dc links as DPIA. The dc link for DPIA is further to be enhanced with implementation for link encoder and link initialization. 2) usb4_dpia_count in struct resource_pool will be initialized to 4 in dcn31_resource_construct() if the DCN is YELLOW_CARP_B0. 3) Enabled DMUB AUX via outbox for YELLOW_CARP_B0. Reviewed-by:
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Jimmy Kizito authored
[Why & How] USB4 endpoints are dynamically mapped. We create additional link encoders for USB4 use when DC is created and destroy them when DC is destructed Reviewed-by:
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Marek Olšák authored
ind_block_64b_no_128bcl means INDEP_64B && INDEP_128B && MAX_COMPRESSED_BLOCK_SIZE == 64B. Only used by gfx10.3. ind_block_64b means INDEP_64B && !INDEP_128B && MAX_COMPRESSED_BLOCK_SIZE == 64B. Only used by gfx9 and gfx10. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Acked-by:
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Leo (Hanghong) Ma authored
[Why] During DQE's promotion test, error appears in dmesg at boot on dcn3.1; [How] Add NULL pointor check for the pointor to the amdgpu_dm_connector; Reviewed-by:
Solomon Chiu <solomon.chiu@amd.com> Signed-off-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by:
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Jimmy Kizito authored
[Why] Trying to enable multiple displays simultaneously exposed shortcomings with the algorithm for dynamic link encoder assignment. The main problems were: - Assuming stream order remained constant across states would sometimes lead to invalid DIG encoder assignment. - Incorrect logic for deciding whether or not a DIG could support a stream would also sometimes lead to invalid DIG encoder assignment. - Changes in encoder assignment were wholesale while updating of the pipe backend is incremental. This would lead to the hardware state not matching the software state even with valid encoder assignments. [How] The following changes fix the identified problems. - Use stream pointer rather than stream index to track streams across states. - Fix DIG compatibility check by examining the link signal type rather than the stream signal type. - Modify assignment algorithm to make incremental updates so software and hardware states remain coherent. Additionally: - Add assertions and an encoder assignment validation function link_enc_cfg_validate() to detect potential problems with encoder assignment closer to their root cause. - Reduce the frequency with which the assignment algorithm is executed. It should not be necessary for fast state validation. Reviewed-by:
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Leo (Hanghong) Ma authored
[Why & How] The codes to blank all dp display have been called many times, so add a helper in dc_link to make it more concise. Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Aric Cyr authored
This version brings along following fixes: - New firmware version - Fix DMUB problems on stress test. - Improve link training by skip overrride for preferred link - Refinement of FPU code structure for DCN2 - Fix 3DLUT skipped programming - Fix detection of 4 lane for DPALT - Fix dcn3 failure due to dmcbu_abm not created - Limit display scaling to up to 4k for DCN 3.1 - Add helper for blanking all dp displays Acked-by:
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Anthony Koo authored
Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Hansen authored
[Why] DPALT detection for B0 PHY has its own set of RDPCSPIPE registers [How] Use RDPCSPIPE registers to detect if DPALT lane is 4 lane Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Hansen <Hansen.Dsouza@amd.com> Signed-off-by:
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Nikola Cornij authored
[why] The existing limit was mistakenly bigger than 4k for DCN 3.1 Reviewed-by:
Zhan Liu <Zhan.Liu@amd.com> Acked-by:
Nikola Cornij <nikola.cornij@amd.com> Signed-off-by:
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Jake Wang authored
[Why & How] Added root clock optimization debug flags for future debugging. Reviewed-by:
Jake Wang <haonan.wang2@amd.com> Signed-off-by:
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Qingqing Zhuo authored
[Why] Current FPU code for DCN2x is located under dml/dcn2x. This is not aligned with DC's general source tree structure. [How] Move FPU code for DCN2x to dml/dcn20. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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George Shen authored
[Why] Overriding link setting inside override_training_settings result in fallback link settings being ignored. This can potentially cause link training to always fail and consequently result in an infinite loop of link training to occur in dp_verify_link_cap during detection. [How] Since preferred link settings are already considered inside decide_link_settings, skip the check in override_training_settings to avoid infinite link training loops. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
George Shen <george.shen@amd.com> Signed-off-by:
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- 05 Oct, 2021 5 commits
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Guchun Chen authored
In current code, when a PCI error state pci_channel_io_normal is detectd, it will report PCI_ERS_RESULT_CAN_RECOVER status to PCI driver, and PCI driver will continue the execution of PCI resume callback report_resume by pci_walk_bridge, and the callback will go into amdgpu_pci_resume finally, where write lock is releasd unconditionally without acquiring such lock first. In this case, a deadlock will happen when other threads start to acquire the read lock. To fix this, add a member in amdgpu_device strucutre to cache pci_channel_state, and only continue the execution in amdgpu_pci_resume when it's pci_channel_io_frozen. Fixes: c9a6b82f ("drm/amdgpu: Implement DPC recovery") Suggested-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Christian König authored
Make sure that we notice this in error reports. Signed-off-by:
Christian König <christian.koenig@amd.com> Acked-by:
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Christian König authored
This reverts commit 728e7e0c. Further discussion reveals that this feature is severely broken and needs to be reverted ASAP. GPU reset can never be delayed by userspace even for debugging or otherwise we can run into in kernel deadlocks. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
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Yifan Zhang authored
This patch is to fix clinfo failure in Raven/Picasso: Number of platforms: 1 Platform Profile: FULL_PROFILE Platform Version: OpenCL 2.2 AMD-APP (3364.0) Platform Name: AMD Accelerated Parallel Processing Platform Vendor: Advanced Micro Devices, Inc. Platform Extensions: cl_khr_icd cl_amd_event_callback Platform Name: AMD Accelerated Parallel Processing Number of devices: 0 Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Tested-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Yifan Zhang authored
kfd_resume doesn't involve iommu operation, remove redundant iommu cleanup code. Signed-off-by:
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- 04 Oct, 2021 6 commits
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Alex Deucher authored
Depends on DRM_AMDGPU_SI and DRM_AMD_DC Reviewed-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Wyatt Wood authored
[Why] Running into bugchecks during stress test where rptr is 0xFFFFFFFF. Typically this is caused by a hard hang, and can come from HW outside of DCN. [How] To prevent bugchecks when writing the DMUB rptr, fist check that the rptr is valid. Reviewed-by:
Wyatt Wood <wyatt.wood@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Alex Deucher authored
No need for a separate kconfig option at this point. Reviewed-by:
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Guo Zhengkui authored
Remove two repeated includings in line 46 and 47. Acked-by:
Guo Zhengkui <guozhengkui@vivo.com> Signed-off-by:
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Lijo Lazar authored
In the rare event when GFX IP suspend coincides with a s0ix entry, don't schedule a delayed work, instead signal PMFW immediately to allow GFXOFF entry. GFXOFF is a prerequisite for s0ix entry. PMFW needs to be signaled about GFXOFF status before amd-pmc module passes OS HINT to PMFW telling that everything is ready for a safe s0ix entry. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1712Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Mario Limonciello <mario.limonciell@amd.com> Signed-off-by:
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