- 18 Aug, 2020 12 commits
-
-
jqdeng authored
Use function printk_ratelimit to limit the print rate. Signed-off-by:
jqdeng <Emily.Deng@amd.com> Acked-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
jqdeng authored
Only for no job running test case need to do recover in flr notification. For having job in mirror list, then let guest driver to hit job timeout, and then do recover. Signed-off-by:
-
Evan Quan authored
Considering the same logic can be applied to Arcturus, Navi1X and Sienna Cichlid. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
-
Evan Quan authored
Add deep sleep disablement/enablement on UMD pstate entering/exiting. Signed-off-by:
-
Evan Quan authored
Considering the same logic can be applied to Arcturus, Navi1X and Sienna Cichlid. Signed-off-by:
-
Evan Quan authored
Add gfx ulv disablement/enablement on UMD pstate entering/exiting. Signed-off-by:
-
Jiansong Chen authored
It's in accordance with pmfw 65.7.0 for navy_flounder. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
-
Jiansong Chen authored
This reverts commit ba4e049e. Newly released sdma fw (51.52) provides a fix for the issue. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
-
Luben Tuikov authored
Remove DRM_SCHED_PRIORITY_INVALID. We no longer carry around an invalid priority and cut it off at the source. Backwards compatibility behaviour of AMDGPU CTX IOCTL passing in garbage for context priority from user space and then mapping that to DRM_SCHED_PRIORITY_NORMAL is preserved. v2: Revert "res" --> "r" and "prio" --> "priority". Signed-off-by:Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
-
Luben Tuikov authored
Remove DRM_SCHED_PRIORITY_LOW, as it was used in only one place. Rename and separate by a line DRM_SCHED_PRIORITY_MAX to DRM_SCHED_PRIORITY_COUNT as it represents a (total) count of said priorities and it is used as such in loops throughout the code. (0-based indexing is the the count number.) Remove redundant word HIGH in priority names, and rename *KERNEL* to *HIGH*, as it really means that, high. v2: Add back KERNEL and remove SW and HW, in lieu of a single HIGH between NORMAL and KERNEL. Signed-off-by: -
Bhawanpreet Lakha authored
Without this, enabling dsc will cause a nullptr Reviewed-by:
Mikita Lipski <Mikita.Lipski@amd.com> Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
-
Mukul Joshi authored
To prevent reporting erroneous SDMA usage, initialize SDMA activity counter to 0 before using. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
-
- 17 Aug, 2020 21 commits
-
-
Bhawanpreet Lakha authored
This field is not defined for DCN3 Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
-
Anthony Koo authored
[Header Changes] - Add command for panel power seq control Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
-
Jaehyun Chung authored
[Why] DSC will be disabled if DPCD 0006F[6:3] is set to a non-zero value because bits 6:3 are not currently supported. When 6:3 is populated, an unsupported INCREMENT OF bits_per_pixel value is read (DPCD 0006F[2:0]) [How] Mask the INCREMENT OF bits_per_pixel field so that values in the unsupported field are ignored. Signed-off-by:
Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
-
Krunoslav Kovac authored
[Why&How] pow(a,x) is implemented as exp(x*log(a)). log(0) will crash. So return 0^x = 0, unless x=0, convention seems to be 0^0 = 1. Cc: stable@vger.kernel.org Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
-
Chris Park authored
[Why] Programming is missing the sequence where for eDP the scrambling is reset when testing for eye diagram test pattern. [How] Include the required register in the definition Signed-off-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
-
Lewis Huang authored
[Why] For some special panel, it will have an invalid HPD high cause driver DPCD read/write fail. [How] Add extra T3 delay as a monitor patch in dce110_edp_wait_for_hpd_ready Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
-
Eryk Brol authored
[why] Previously when force enabling DSC on SST display we unknowingly supressed lane count, which caused DSC to be enabled automatically. [how] By adding an additional flag to force enable DSC in dc_dsc.c DSC can always be enabled with debugfs dsc_clock_en forced to 1 Cc: stable@vger.kernel.org Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Signed-off-by:
-
Dmytro Laktyushkin authored
Wide timing DSC requires odm. Since spreadsheet is missing this dsc validation we have to modify DML vba code ourselves. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
-
Qingqing Zhuo authored
[why] Current pipe merge and split logic only supports cases where new dc_state is allocated and relies on dc->current_state to gather information from previous dc_state. Calls to validate_bandwidth on UPDATE_TYPE_MED would cause an issue because there is no new dc_state allocated, and data in dc->current_state would be overwritten during pipe merge. [how] Only allow validate_bandwidth when new dc_state space is created. Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
-
Yongqiang Sun authored
[Why & How] Add read backlight interface to get ABM data. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
-
hersen wu authored
[Why] with eDP + DP, each display use one pipe. after DP unplugged, eDP switch from one pipe to two pipes -- pipe split. dpp1_cm_set_regamma_pwl will be executed too. The duration from switch single pipe to dual pipes is a little long which could let eDP enter PSR mode. upon two pipes for eDP are setup, eDP PHY is disabled. front pipe is not really running to fetch data from frame buffer. i.e., dchubp is not in normal working status. execution of hubbub1_wm_change_req_wa may cause p-state warning. [How] disable eDP PSR before dc_commit_state. psr is disabled when execute hubbub1_wm_change_req_wa. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
-
Paul Hsieh authored
[Why] Place the cursor in the center of screen between two pipes then adjusting the viewport but cursour doesn't update cause DFPstate hang. [How] If viewport changed, update cursor as well. Cc: stable@vger.kernel.org Signed-off-by:
Paul Hsieh <paul.hsieh@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
-
Yongqiang Sun authored
[Why & How] change abm config init interface to support multiple ABMs. Signed-off-by:
-
Wenjing Liu authored
[why] create a dedicated function to make mst link settings decision, so that the policy's decision is made in a unified place. Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
-
Chris Park authored
[Why] Reading for DP alt registers return incorrect values due to LE_SF definition missing. [How] Define correct LE_SF or DP alt registers. Signed-off-by:
-
Chris Park authored
[Why] If DMUB is used, LVTMA VBIOS call can be used to control eDP instead of tranditional transmitter control. Interface is agreed with VBIOS for eDP to use this new path to program LVTMA registers. [How] Create DAL interface to send DMUB command for LVTMA as currently implemented in VBIOS. Signed-off-by:
-
Anthony Koo authored
Signed-off-by:
-
Anthony Koo authored
Signed-off-by:
-
Kevin Wang authored
v1: add trace event enabled check to avoid nop loop when submit multi ibs in amdgpu_cs_ioctl() function. v2: add a new wrapper function to trace all amdgpu cs ibs. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
-
Kevin Wang authored
fix amdgpu_bo_release_notify() comment error. Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Acked-by:
-
Huang Rui authored
Renoir only has one sdma instance, it will get failed once query the sdma1 registers. So use switch-case instead of static register array. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
-
- 14 Aug, 2020 7 commits
-
-
Alex Deucher authored
The caller does this now for all reset types. This is now a duplicate call. Reviewed-by:
-
Alex Deucher authored
When we reset the GPU, note what type of reset will be used. This makes debugging different reset scenarios more clear as the driver may use different reset methods depending on conditions on the system. Acked-by:
-
Alex Deucher authored
ACPI, ROM, PCI BAR, etc. Acked-by:
-
Bhawanpreet Lakha authored
Use the same case as sienna_cichlid Signed-off-by:
-
James Zhu authored
Only SIENNA_CICHLID(VCN3) has 2 unsymmetrical instances, there're less codecs on instance 1, we use 0 for decode and 1 for encode. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
-
Evan Quan authored
The target is to provide a clear entry point(for power routines). Also this can help to maintain a clear view about the frameworks used on different ASICs. Hopefully all these can make power part more friendly to play with. Signed-off-by:
-
Evan Quan authored
As other power interfaces. Signed-off-by:
-
