- 04 Oct, 2022 1 commit
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Stephen Boyd authored
Merge tag 'qcom-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clk driver updates from Bjorn Andersson: This introduces display clock controllers are introduces for SM6115 and SM8450, and SC8280XP gains a GPU clock controller. MSM8909 and SM6375 gains global and SMD RPM clock controller drivers. The handling of GDSCs with PWRSTS_RET was fixed, to keep the GDSC on while powering down the parent supply. This solved retention issues during suspend of USB on sc7180/7280 and SC8280XP. SM6115 and QCM2260 are moved to reuse PLL configuration. SDM660 SDCC1 was moved to floor ops. Support for the APCS PLLs for IPQ8064, IPQ8074 and IPQ6018 was added/fixed. The MSM8996 CPU clocks was updated, with support for ACD clocks added. Support for SDM670 was added to the SDM845 Glbal clock controller and the RPMh clock controller driver. Transition to parent_data, parent_hws and use of ARRAY_SIZE() for num_parents was done for MSM8660, MSM8916, MSM8939, MSM8960 global clock controllers, IPQ8064 LPASS clock controller and MSM8960 multimedia clock controller. Support for per-reset defined delay of was introduced. * tag 'qcom-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (93 commits) clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-msm8939: use parent_hws where possible dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml clk: qcom: gcc-sm6350: Update the .pwrsts for usb gdscs clk: qcom: gcc-sc8280xp: use retention for USB power domains clk: qcom: gdsc: add missing error handling dt-bindings: clocks: qcom,gcc-sc8280xp: Fix typos clk: qcom: Add global clock controller driver for SM6375 dt-bindings: clock: add SM6375 QCOM global clock bindings clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bit clk: qcom: gcc-sc7280: Update the .pwrsts for usb gdscs clk: qcom: gcc-sc7180: Update the .pwrsts for usb gdsc clk: qcom: gdsc: Fix the handling of PWRSTS_RET support clk: qcom: Add SC8280XP GPU clock controller dt-bindings: clock: Add Qualcomm SC8280XP GPU binding clk: qcom: smd: Add SM6375 clocks dt-bindings: clock: qcom: rpmcc: Add BIMC_FREQ_LOG dt-bindings: clock: qcom,rpmcc: Add compatible for SM6375 clk: qcom: rpmhcc: add sdm670 clocks dt-bindings: clock: add rpmhcc bindings for sdm670 ...
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- 29 Sep, 2022 6 commits
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220928145609.375860-4-dmitry.baryshkov@linaro.org
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Dmitry Baryshkov authored
Use parent_hws instead of hanving parent_data with just a single .hw entry to speed up and simplify parent lookups. Signed-off-by:
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Dmitry Baryshkov authored
The MSM8939 GCC bindings are fully comptible with MSM8916, the clock controller requires the same parent clocks, move MSM8939 GCC compatible to qcom,msm8916.yaml Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Luca Weiss authored
The USB controllers on sm6350 do not retain the state when the system goes into low power state and the GDSCs are turned off. This can be observed by the USB connection not coming back alive after putting the device into suspend, essentially breaking USB. Fix this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. Cc: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Signed-off-by:
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Johan Hovold authored
Since commit d3997239 ("clk: qcom: gdsc: Fix the handling of PWRSTS_RET support) retention mode can be used on sc8280xp to maintain state during suspend instead of leaving the domain always on. This is needed to eventually allow the parent CX domain to be powered down during suspend. Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
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Johan Hovold authored
Since commit 7eb231c3 ("PM / Domains: Convert pm_genpd_init() to return an error code") pm_genpd_init() can return an error which the caller must handle. The current error handling was also incomplete as the runtime PM and regulator use counts were not balanced in all error paths. Add the missing error handling to the GDSC initialisation to avoid continuing as if nothing happened on errors. Signed-off-by:
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- 28 Sep, 2022 7 commits
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Andrew Halaney authored
pipegmux and SuperSpeed are the proper spelling for those terms. Signed-off-by:
Andrew Halaney <ahalaney@redhat.com> Acked-by:
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Konrad Dybcio authored
Add support for the global clock controller found on SM6375. Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Konrad Dybcio authored
Add device tree bindings for global clock controller for SM6375 SoCs. Signed-off-by:
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Konrad Dybcio authored
This is used on at least SM6375 and its variations. Signed-off-by:
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Rajendra Nayak authored
The USB controllers on sc7280 do not retain the state when the system goes into low power state and the GDSCs are turned off. This results in the controllers reinitializing and re-enumerating all the connected devices (resulting in additional delay while coming out of suspend) Fix this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. Since sc7280 only supports cx (parent of usb gdscs) Retention, there are no cxcs offsets mentioned in order to support the Retention state. Signed-off-by:
Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by:
Matthias Kaehlcke <mka@chromium.org> Tested-by:
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Rajendra Nayak authored
The USB controller on sc7180 does not retain the state when the system goes into low power state and the GDSC is turned off. This results in the controller reinitializing and re-enumerating all the connected devices (resulting in additional delay while coming out of suspend) Fix this by updating the .pwrsts for the USB GDSC so it only transitions to retention state in low power. Since sc7180 only supports cx (parent of usb gdsc) Retention, there are no cxcs offsets mentioned in order to support the Retention state. Signed-off-by:
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Rajendra Nayak authored
GDSCs cannot be transitioned into a Retention state in SW. When either the RETAIN_MEM bit, or both the RETAIN_MEM and RETAIN_PERIPH bits are set, and the GDSC is left ON, the HW takes care of retaining the memory/logic for the domain when the parent domain transitions to power collapse/power off state. On some platforms where the parent domains lowest power state itself is Retention, just leaving the GDSC in ON (without any RETAIN_MEM/RETAIN_PERIPH bits being set) will also transition it to Retention. The existing logic handling the PWRSTS_RET seems to set the RETAIN_MEM/RETAIN_PERIPH bits if the cxcs offsets are specified but then explicitly turns the GDSC OFF as part of _gdsc_disable(). Fix that by leaving the GDSC in ON state. Signed-off-by:
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- 27 Sep, 2022 25 commits
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Bjorn Andersson authored
Add driver for the GPU clock controller in the Qualcomm SC8280XP platform. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by:
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Bjorn Andersson authored
Add compatible for the Qualcomm SC8280XP GPU. Signed-off-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
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Konrad Dybcio authored
Add support for controlling SMD RPM clocks on SM6375. Signed-off-by:
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Konrad Dybcio authored
Add the missing definition for the aforementioned clock. Signed-off-by:
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Konrad Dybcio authored
Add a compatible for RPMCC on SM6375. Signed-off-by:
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Richard Acayan authored
The Snapdragon 670 uses the RPMh mailbox for most of the clocks used in SDM845 but omits two. Add clock data for SDM670 so the driver doesn't fail to resolve a clock. Link: https://android.googlesource.com/kernel/msm/+/443bd8d6e2cf54698234c752e6de97b4b8a528bd%5E%21/#F7Signed-off-by:
Richard Acayan <mailingradian@gmail.com> Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Richard Acayan authored
The Snapdragon 670 uses the RPMh mailbox for some clocks. Document its support. Signed-off-by:
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Krzysztof Kozlowski authored
Emails to codeaurora.org bounce ("Recipient address rejected: undeliverable address: No such user here."). Signed-off-by:Rob Herring <robh@kernel.org> Signed-off-by:
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Iskren Chernev authored
The qcom2260 and sm6115 GCC drivers use a common modified DEFAULT and BRAMMO alpha pll offsets. Move these common offsets to the shared place to avoid duplication. The new layouts have a suffix EVO similar to LUCID and RIVIAN. Signed-off-by:
Iskren Chernev <iskren.chernev@gmail.com> Signed-off-by:
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Iskren Chernev authored
sm6115 uses a modified default and bramo alpha pll offsets. Put them in the same place for consistency. Signed-off-by:
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Adam Skladowski authored
The DEFAULT and BRAMMO PLL offsets are non-standard in downstream, but currently only BRAMMO ones are overridden. Override DEFAULT ones too. A very similar thing is happening in gcc-qcm2290 driver. Fixes: cbe63bfd ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by:
Adam Skladowski <a_skl39@protonmail.com> Signed-off-by:
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Dmitry Baryshkov authored
Add support for the dispcc on Qualcomm SM8450 platform. Signed-off-by:
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Dmitry Baryshkov authored
PLLs can be kept in standby (default configuration) or in off mode when disabled during power collapse. Hence add support for pll disable off mode for lucid evo PLL. Signed-off-by:
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Dmitry Baryshkov authored
Add device tree bindings for the display clock controller on Qualcomm SM8450 platform. Signed-off-by:
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Adam Skladowski authored
Add support for the display clock controller found in SM6115/SM4250 based devices. This clock controller feeds the Multimedia Display SubSystem (MDSS). This driver is based upon one submitted for QCM2290. Signed-off-by:
Adam Skladowski <a39.skl@gmail.com> Signed-off-by:
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Adam Skladowski authored
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6115 SoC. Signed-off-by:
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Krishna chaitanya chundru authored
Enabling PCIe GDSC retention to ensure controller and its dependent clocks won't go down during system suspend. Update the .pwrsts for PCIe GDSC so it only transitions to RET in low power. Signed-off-by:
Krishna chaitanya chundru <quic_krichai@quicinc.com> Signed-off-by:
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Satya Priya authored
Change the qcom_cc_probe_by_index() call to qcom_cc_really_probe() to avoid remapping of memory region for index 0, which is already being done through qcom_cc_map(). Fixes: 7c6a6641 ("clk: qcom: lpass: Add support for resets & external mclk for SC7280") Signed-off-by:
Satya Priya <quic_c_skakit@quicinc.com> Reviewed-by:
Neil Armstrong <neil.armstrong@baylibre.com> Signed-off-by:
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Robert Marko authored
Add support for IPQ8074 since it uses the same PLL setup, however it uses slightly different Alpha PLL config. Alpha PLL config was obtained by dumping PLL registers from a running device. Signed-off-by:
Robert Marko <robimarko@gmail.com> Signed-off-by:
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Robert Marko authored
Update the IPQ6018 Alpha PLL config to the latest one from the downstream 5.4 kernel[1]. This one should match the production SoC-s. Tested on IPQ6018 CP01-C1 reference board. [1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.1.r4/drivers/clk/qcom/apss-ipq-pll.c#L41Signed-off-by:
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Robert Marko authored
Convert the driver to use OF match data for providing the Alpha PLL config per compatible. This is required for IPQ8074 support since it uses a different Alpha PLL config. While we are here rename "ipq_pll_config" to "ipq6018_pll_config" to make it clear that it is for IPQ6018 only. Signed-off-by:
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Robert Marko authored
Add IPQ8074 compatible to A53 PLL bindings. Signed-off-by:
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Robert Marko authored
While fixing up the driver I noticed that my IPQ8074 board was hanging after CPUFreq switched the frequency during boot, WDT would eventually reset it. So mark apcs_alias0_core_clk as critical since its the clock feeding the CPU cluster and must never be disabled. Fixes: 5e77b4ef ("clk: qcom: Add ipq6018 apss clock controller") Signed-off-by:
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Robert Marko authored
While working on IPQ8074 APSS driver it was discovered that IPQ6018 and IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is currently broken. More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux clock. However after debugging why it was always stuck at 800Mhz, it was figured out that its not regmap_mux compatible at all. It is a simple mux but it uses RCG2 register layout and control bits, so utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not having to provide a dummy frequency table. While we are here, use ARRAY_SIZE for number of parents. Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards. Fixes: 5e77b4ef ("clk: qcom: Add ipq6018 apss clock controller") Signed-off-by:
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Christian Marangi authored
An RCG may act as a mux that switch between 2 parents. This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds the CPU cluster clock just switches between XO and the PLL that feeds it. Add the required ops to add support for this special configuration and use the generic mux function to determine the rate. This way we dont have to keep a essentially dummy frequency table to use RCG2 as a mux. Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Signed-off-by:
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- 26 Sep, 2022 1 commit
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Christian Marangi authored
Use ARRAY_SIZE for num_parents instead of raw number to prevent any confusion/mistake. Signed-off-by:
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