* clk-qcom:
  clk: qcom: clk-smd-rpm: add msm8996 rpmclks
  clk: qcom: Implement RPM clocks for MSM8660/APQ8060
  clk: qcom: Update DT bindings for the MSM8660/APQ8060 RPMCC
  clk: qcom: Elaborate on "active" clocks in the RPM clock bindings
  clk: qcom: Remove unused RCG ops

* clk-at91:
  clk: at91: utmi: set the mainck rate

* clk-devm-provider:
  clk: qcom: common: Migrate to devm_* APIs for resets and clk providers
  clk: Add devm_of_clk_add_hw_provider()/del_provider() APIs

* clk-const:
  clk: make clk_init_data const
  clk: imx: make clk_ops const
  clk: mmp: make clk_ops const
  clk: hisilicon: make clk_ops const
  clk: mxs: make clk_ops const
  clk: sirf: make clk_ops const
  clk: spear: make clk_ops const
  CLK: SPEAr: make aux_clk_masks structures const
  CLK: SPEAr: make structure field and function argument as const

* clk-sunxi:
  clk: sunxi: explicitly request exclusive reset control
  clk: sunxi: fix build warning

* clk-hikey:
  clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu'
  clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep()
  clk: hi3660: fix incorrect uart3 clock freqency
  clk: hi6220: mark clock cs_atb_syspll as critical

Merge tag 'tegra-for-4.15-clk-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next

Pull tegra clk drivers updates from Thierry Reding:

This contains cleanups and minor fixes for the Tegra clock driver.

* tag 'tegra-for-4.15-clk-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()
  clk: tegra: dfll: Fix drvdata overwriting issue
  clk: tegra: Fix cclk_lp divisor register
  clk: tegra: Bump SCLK clock rate to 216 MHz
  clk: tegra: Use common definition of APBDMA clock gate
  clk: tegra: Correct parent of the APBDMA clock
  clk: tegra: Add AHB DMA clock entry
  clk: tegra: Mark APB clock as critical
  clk: tegra: Make tegra_clk_pll_params __ro_after_init
  clk: tegra: Fix sor1_out clock implementation
  clk: tegra: Use tegra_clk_register_periph_data()
  clk: tegra: Add peripheral clock registration helper
  clk: tegra: Check BPMP response return code
  dt-bindings: clock: tegra: Add sor1_out clock
  firmware: tegra: Propagate error code to caller

Other than 'mmc_mux', 'clk_sdio0_ciu' uses a different parent mux clock.
Let's add this mux clock as 'sdio0_mux', and correct the parent of
'clk_sdio0_ciu' to be it.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep()

Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Reviewed-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

UART3 clock rate is doubled in previous commit.

This error is not detected until recently a mezzanine board which makes
real use of uart3 port (through LS connector of 96boards) was setup
and tested on hi3660-hikey960 board.

This patch changes clock source rate of clk_factor_uart3 to 100000000.
Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Add all RPM controlled clocks on msm8996 platform

[srini: Fixed various issues with offsets and made names specific to msm8996]
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

The RPM clocks were missing for MSM8660/APQ8060. For this to be
completed we need to add a special fixed rate RPM clock that is used
for the PLL4 on these SoCs. The rest of the clocks are pretty
similar to the other supported platforms.

The "active" clock pattern is mirrored in all the clocks. I guess
that the PLL4 that clocks the LPASS is actually never used as
"active only" since the low-power audio subsystem should be left
on when the CPU goes to idle, so that it can be used as a stand-alone
MP3 player type of device.

The PLL4 seems to be enabled only on behalf of the booting LPASS
Hexagon - which will cast its own vote once its booted - and as
such we only configure the active state (meaning both states will
have same configuration). The result is that PLL4 will be on
from prepare() to unprepare() regardless of what the application
CPU does.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

These compatible strings need to be added to extend support
for the RPM CC to cover MSM8660/APQ8060. We also need to add
enumberators to the include file for a few clocks that were
missing.

Cc: devicetree@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

The concept of "active" clocks is just explained in a bried comment in the
device driver, let's explain it a bit more in the device tree bindings
so everyone understands this.

Cc: devicetree@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

The RCGs ops for shared branches are not used now, so remove it.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

By default, it is assumed that the UTMI clock is generated from a 12 MHz
reference clock (MAINCK). If it's not the case, the FREQ field of the
SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the
proper way.

The UTMI clock has a fixed rate of 480 MHz. In fact, there is no
multiplier we can configure. The multiplier is managed internally,
depending on the reference clock frequency, to achieve the target of
480 MHz.
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Acked-by: Ingo van Lil <inguin@gmx.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Now that we have devm APIs for the reset controller and of clk hw
provider APIs we can remove the custom code here.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Sometimes we only have one of_clk_del_provider() call in driver
error and remove paths, because we're missing a
devm_of_clk_add_hw_provider() API. Introduce the API so we can
convert drivers to use this and potentially reduce the amount of
code needed to remove providers in drivers.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Make these const as they are only stored in the init field of a clk_hw
structure, which is const.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Make these const as they are only stored in the const field of a
clk_init_data structure.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Make these const as they are only stored in the const field of a
clk_init_data structure.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Make these const as they are only stored in the const field of a
clk_init_data structure.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Make these const as they are only stored in the const field of a
clk_init_data structure.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Make these const as they are only stored in the const field of a
clk_init_data structure.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Make these const as they are only stored in the const field of a
clk_init_data structure.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Make these const as they are either stored in the masks 'const' field
of a clk_aux structure or passed to the function clk_register_aux
having the argument as const.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Make the masks field of clk_aux structure const as it do not modify the
fields of the aux_clk_masks structure it points to.

Make the struct aux_clk_masks *aux argument of the function
clk_register_aux as const as the argument is only stored in the masks
field of a clk_aux structure which is now made const.
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Commit a53e35db ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control request API calls
to explicitly state whether the driver needs exclusive or shared reset
control behavior. Convert all drivers requesting exclusive resets to the
explicit API call so the temporary transition helpers can be removed.

No functional changes.

Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

This patch fix the following build warning:
drivers/clk/sunxi/clk-factors.c:279:14: warning: variable 'name' set but not used [-Wunused-but-set-variable]

Fixes: 4cbeaebb ("clk: sunxi: factors: Add unregister function")
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Clock cs_atb_syspll is pll used for coresight trace bus; when clock
cs_atb_syspll is disabled and operates its child clock node cs_atb
results in system hang. So mark clock cs_atb_syspll as critical to
keep it enabled.

Cc: Guodong Xu <guodong.xu@linaro.org>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1504226835-2115-2-git-send-email-leo.yan@linaro.org

Below is the call trace of tegra210_init_pllu() function:
  start_kernel()
  -> time_init()
  --> of_clk_init()
  ---> tegra210_clock_init()
  ----> tegra210_pll_init()
  -----> tegra210_init_pllu()

Because the preemption is disabled in the start_kernel before calling
time_init, tegra210_init_pllu is actually in an atomic context while
it includes a readl_relaxed_poll_timeout that might sleep.

So this patch just changes this readl_relaxed_poll_timeout() to its
atomic version.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Both tegra124-dfll and clk-dfll are using platform_set_drvdata
to set drvdata of the exact same pdev while they use different
pointers for the drvdata. Once the drvdata has been overwritten
by tegra124-dfll, clk-dfll will never get its td pointer as it
expects.

Since tegra124-dfll merely needs its soc pointer in its remove
function, this patch fixes the bug by removing the overwriting
in the tegra124-dfll file and letting the tegra_dfll_unregister
return an soc pointer for it.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

According to comments in code and common sense, cclk_lp uses its
own divisor, not cclk_g's.

Fixes: b08e8c0e ("clk: tegra: add clock support for Tegra30")
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

AHB DMA is a running on 1/2 of SCLK rate, APB DMA on 1/4. Increasing SCLK
rate results in an increased DMA transfer rate.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

The APBDMA clock is defined in the common clock gates table that is used
by Tegra30+. Tegra20 can use it too, let's remove the custom definition
and use the common one.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

APBDMA represents a clock gate to the APB DMA controller, the actual
clock source for the controller is PCLK.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

AHB DMA engine presents on Tegra20/30. Add missing clock entries, so that
driver for the AHB DMA controller could be implemented.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Currently, the APB clock is registered with the CLK_IGNORE_UNUSED flag
to prevent the clock from being disabled if unused on boot. However,
even if it is used, it still needs to be always kept enabled so that it
doesn't get inadvertently disabled when all of its children are, and so
update the flag for the APB clock to be CLK_IS_CRITICAL.
Suggested-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Merge tag 'v4.15-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull Rockchip clk drivers updates from Heiko Stuebner:

 - new clock ids for rk3188 and rk3368
 - removal of a superfluous memory allocation error message

* tag 'v4.15-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: use new cif/vdpu clock ids on rk3188
  clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs
  clk: rockchip: add more rk3188 graphics clock ids
  clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs
  clk: rockchip: Remove superfluous error message in rockchip_clk_register_cpuclk()

Merge tag 'clk-renesas-for-v4.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Add support for the second display unit clock on RZ/G1E,
  - Add git repository to MAINTAINERS,
  - Add suspend/resume support for R-Car Gen3 CPG/MSSR,
  - Small fixes and cleanups.

* tag 'clk-renesas-for-v4.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: rcar-gen3: Restore R clock during resume
  clk: renesas: rcar-gen3: Restore SDHI clocks during resume
  clk: renesas: div6: Restore clock state during resume
  clk: renesas: cpg-mssr: Add support to restore core clocks during resume
  clk: renesas: cpg-mssr: Restore module clocks during resume
  MAINTAINERS: Add git repository to Renesas clock driver section
  clk: renesas: cpg-mssr: Add du1 clock to R8A7745
  clk: renesas: rz: clk-rz is meant for RZ/A1
  clk: renesas: r8a77995: Correct parent clock of INTC-AP
  clk: renesas: r8a7796: Correct parent clock of INTC-AP
  clk: renesas: r8a7795: Correct parent clock of INTC-AP