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  1. 15 Dec, 2010 1 commit
  3. 06 Dec, 2010 10 commits
    • Will Deacon's avatar
      ARM: hw_breakpoint: fix warnings generated by sparse · 4a55c18e
      Will Deacon authored 
      sparse doesn't like per-cpu accesses such as:

static DEFINE_PER_CPU(struct perf_event *, foo[MAXLEN]);
struct perf_event **bar = __get_cpu_var(foo);

and shouts quite loudly about it:

| warning: incorrect type in assignment (different modifiers)
|    expected struct perf_event **slots
|    got struct perf_event *[noderef] *<noident>

This patch adds casts to these sorts of assignments in hw_breakpoint.c
in order to silence the warnings.
Reported-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      4a55c18e
    • Will Deacon's avatar
      ARM: ptrace: fix style issue with hw_breakpoint interface · ce9b1b09
      Will Deacon authored 
      This patch fixes a trivial style issue in ptrace.c.
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      ce9b1b09
    • Will Deacon's avatar
      ARM: hw_breakpoint: disallow per-cpu breakpoints without overflow handler · 3ce70b2e
      Will Deacon authored 
      Single-stepping a breakpoint requires us to disable it temporarily so that
we don't get stuck in a recursive debug trap. With per-cpu breakpoints this
presents a problem where an interrupt can be taken before the single-step has
completed and a new task is eventually scheduled. This new task will not
hit the breakpoint because it will have been disabled during the previous
handling code.

This patch disallows per-cpu breakpoints on ARM when an overflow handler
is not present. A similar effect can be created by placing breakpoints on
a shell and then running applications there.
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      3ce70b2e
    • Will Deacon's avatar
      ARM: hw_breakpoint: unify single-stepping code for watchpoints and breakpoints · 9ebb3cbc
      Will Deacon authored 
      The single-stepping code is currently different depending on whether
we are stepping over a breakpoint or a watchpoint. There is no good
reason for this, so let's sort it out.

This patch adds functions for enabling/disabling single-step for
a particular hw_breakpoint and integrates this with the exception
handling code.
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      9ebb3cbc
    • Will Deacon's avatar
      ARM: hw_breakpoint: do not allocate new breakpoints with preemption disabled · 93a04a34
      Will Deacon authored 
      The watchpoint single-stepping code calls register_user_hw_breakpoint to
register a mismatch breakpoint for stepping over the watchpoint. This is
performed with preemption disabled, which is unsafe as we may end up scheduling
whilst in_atomic(). Furthermore, using the perf API is rather overkill since
we are already in the hw-breakpoint backend and only require access to reserved
breakpoints anyway.

This patch reworks the watchpoint stepping code so that we don't require
another perf_event for the mismatch breakpoint. Instead, we hold a separate
arch_hw_breakpoint_ctrl struct inside the watchpoint which is used exclusively
for stepping. We can check whether or not stepping is enabled when installing
or uninstalling the watchpoint and operate on the breakpoint accordingly.
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      93a04a34
    • Will Deacon's avatar
      ARM: hw_breakpoint: don't advertise reserved breakpoints · 0017ff42
      Will Deacon authored 
      To permit handling of watchpoint exceptions without signalling a
debugger, it is necessary to reserve breakpoint registers for in-kernel
use only.

This patch ensures that we record and subtract the number of reserved
breakpoints from the number of usable breakpoint registers that we
advertise to userspace via the ptrace API.
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      0017ff42
    • Will Deacon's avatar
      ARM: hw_breakpoint: disable preemption during debug exception handling · 7e202696
      Will Deacon authored 
      On ARM, debug exceptions occur in the form of data or prefetch aborts.
One difference is that debug exceptions require access to per-cpu banked
registers and data structures which are not saved in the low-level exception
code. For kernels built with CONFIG_PREEMPT, there is an unlikely scenario
that the debug handler ends up running on a different CPU from the one
that originally signalled the event, resulting in random data being read
from the wrong registers.

This patch adds a debug_entry macro to the low-level exception handling
code which checks whether the taken exception is a debug exception. If
it is, the preempt count for the faulting process is incremented. After
the debug handler has finished, the count is decremented.
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      7e202696
    • Will Deacon's avatar
      ARM: hw_breakpoint: correct and simplify alignment fixup code · 6ee33c27
      Will Deacon authored 
      The current hw_breakpoint code tries to fix up the alignment of
breakpoints so that we can make use of sparse byte-address-select
bits in the control register and give the illusion that we can
set breakpoints on unaligned addresses.

Although this works on v6 cores, v7 forbids this behaviour, instead
requiring breakpoints to be set on aligned addresses and have contiguous
byte-address-select ranges depending on the instruction set in use.
For ARM the only supported size is 4 bytes, whilst Thumb-2 also permits
2 byte breakpoints (watchpoints can be of 1, 2, 4 or 8 bytes long).

This patch simplifies the alignment fixup code so that we require
addresses to be aligned to the size of the corresponding breakpoint.
This allows us to handle the common case of breaking on a half-word
aligned Thumb-2 instruction and also allows us to set byte watchpoints
on arbitrary addresses.
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      6ee33c27
    • Will Deacon's avatar
      ARM: hw_breakpoint: reset control registers in hotplug path · 7d99331e
      Will Deacon authored 
      The ARMv7 debug architecture doesn't make any guarantees about the
contents of debug control registers following a debug logic reset.

This patch ensures that we reset the control registers when a cpu
comes ONLINE (for example, with hotplug) so that when we enable
monitor mode while inserting a breakpoint we won't exhibit random
behaviour.
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      7d99331e
    • Will Deacon's avatar
      ARM: hw_breakpoint: ensure OS lock is clear before writing to debug registers · ac88e071
      Will Deacon authored 
      ARMv7 architects a system for saving and restoring the debug registers
across low-power modes. At the heart of this system is a lock register
which, when set, forbids writes to the debug registers. While locked,
writes to debug registers via the co-processor interface will result
in undefined instruction traps. Linux currently doesn't make use of
this feature because we update the debug registers on context switch
anyway, however the status of the lock is IMPLEMENTATION DEFINED on
reset.

This patch ensures that the lock is cleared during boot so that we
can write to the debug registers safely.
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      ac88e071
  5. 30 Nov, 2010 2 commits
  7. 29 Nov, 2010 18 commits
  9. 28 Nov, 2010 9 commits
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