- 05 Jul, 2018 40 commits
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Evan Quan authored
Make sure the clock level set only on dpm enabled. Also uvd/vce/soc clock also changed correspondingly. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Evan Quan authored
So that we do not need to use PPSMC_MSG_GetMin/MaxDpmFreq to get the clock ranges on runtime. Since that causes some problems. Signed-off-by:
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Evan Quan authored
Initialize the soft/hard min/max level correctly and handle the dpm disabled situation. Signed-off-by:
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Evan Quan authored
This workaround is not needed any more. Signed-off-by:
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Evan Quan authored
A new member Vr2_I2C_address is added. Signed-off-by:
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Evan Quan authored
The vbios firmware structure changed between v3_1 and v3_2. So, the code to setup bootup values needs different paths based on header version. Signed-off-by:
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Rex Zhu authored
change wm_min_memg_clk_in_khz -> wm_min_mem_clk_in_khz Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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rex zhu authored
use ppfeaturemask to enable/disable stutter mode. Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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rex zhu authored
Enable stutter mode can save power in low DRAM use cases including but not limited to productivity application use, web browsing, and video playback. Currently this feature is disabled by default. Make bit 17 in module parameter amdgpu_pp_feature_mask as stutter mode mask, so user can enable/disable this feature easily. Reviewed-by:
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Rex Zhu authored
Partially revert commit 2dc80b00 ("drm/amdgpu: optimize amdgpu driver load & resume time")' 1. CG/PG enablement are part of gpu hw ip initialize, we should wait for them complete. otherwise, there are some potential conflicts, for example, Suspend and CG enablement concurrently. 2. better run ib test after hw initialize completely. That is to say, ib test should be after CG/PG enablement. otherwise, the test will not cover the cg/pg/poweroff enable case. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Rex Zhu authored
1. add amdgpu_device_ip_late_set_pg_state function for set pg state. 2. delete duplicate pg state setting on gfx_v8_0's late_init. Reviewed-by:
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Rex Zhu authored
we can take gfx off feature as gfx power gate. gfx off feature is also controled by smu. so add gfx_off support in pp_set_powergating_by_smu. Reviewed-by:
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Rex Zhu authored
Raven support gfx off feature instand of gfx powergate, so use smu10_gfx_off_control as the powergate_gfx backend function. Reviewed-by:
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Rex Zhu authored
gfx ip block can call set_powergating_by_smu to set gfx pg state if necessary. Reviewed-by:
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Rex Zhu authored
Some HW ip blocks need call SMU to enter/leave power gate state. So export common set_powergating_by_smu interface. 1. keep consistent with set_clockgating_by_smu 2. scales easily to powergate other ip(gfx) if necessary Reviewed-by:
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Rex Zhu authored
keep consistent with powergate_uvd/vce/mmhub Reviewed-by:
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Rex Zhu authored
In order to keep consistent with powergate_uvd/vce. Reviewed-by:
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rex zhu authored
fix a typo when convert displayphyclk type. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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rex zhu authored
powerplay implement hwmgr_function table for all supported asics in order to conceal the asic's detail infomation. so no need to include the smu10_hwmgr.h. Reviewed-by:
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Flora Cui authored
the fence_context and seqno is init in amdgpu_vm_manager_init() & amdgpu_vmid_mgr_init(). remove the amdgpu_vmid_mgr_init() copy. Signed-off-by:
Flora Cui <Flora.Cui@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Stefan Agner authored
The wrong enum type is used to initialize the result, leading to a warning when using clang: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:1998:26: warning: implicit conversion from enumeration type 'enum ddc_result' to different enumeration type 'enum dc_status' [-Wenum-conversion] enum dc_status result = DDC_RESULT_UNKNOWN; ~~~~~~ ^~~~~~~~~~~~~~~~~~ 1 warning generated. Initialization of result is unnecessary anyway, just drop the initialization. Signed-off-by:Stefan Agner <stefan@agner.ch> Reviewed-by:
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Andrey Grodzovsky authored
Everything in the flush code path (i.e. waiting for SW queue to become empty) names with *_flush() and everything in the release code path names *_fini() Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Suggested-by:
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Andrey Grodzovsky authored
Everything in the flush code path (i.e. waiting for SW queue to become empty) names with *_flush() and everything in the release code path names *_fini() This patch also effect the amdgpu and etnaviv drivers which use those functions. v2: Also pplay the change to vd3. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
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Tony Cheng authored
use worse case watermark (consider both DCC and VM) to keep golden consistent regardless of DCC Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Samson Tam authored
Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Reviewed-by:
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Tony Cheng authored
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Yongqiang Sun authored
In case of roation, width and height in viewport is difference between viewport and h_active and v_active, while this is not scaling. The right way is check ratios in scaling data, to determine it is a scaling case or not. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
Currently dcn1 will not switch between watermark sets so we can save time by not calculating 3 extra sets. Signed-off-by:
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Dmytro Laktyushkin authored
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Mikita Lipski authored
Moving powerplay functions to a new amdgpu_dm_pp_smu class and cleaning dm_services class from unused headers. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Signed-off-by:
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Mikita Lipski authored
The driver is expecting clock frequency in kHz, while SMU returns the values in 10kHz, which causes the bandwidth validation to fail Signed-off-by:
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Mikita Lipski authored
Add more cases for dm_pp clks translator into pp clks so we can pass the right structures to the powerplay. Use clks translator instead of massive switch statement. Signed-off-by:
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Mikita Lipski authored
Set the powerplay debug flag to false for both Windows and Linux to allow the calls to pplib. So we can retrieve the clock values from powerplay instead of using default hardcoded values. Signed-off-by:
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Roman Li authored
- Fixing integer overflow bug in wait_for_fbc_state_changed() - Correct the max value of retries for the corresponding warning Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Tony Cheng authored
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