- 10 Jan, 2023 11 commits
-
-
Neil Armstrong authored
Add support for the display clock controller found in SM8550 based devices. This clock controller feeds the Multimedia Display SubSystem (MDSS). This driver is based on the SM8450 support. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-dispcc-v3-3-8a03d348c572@linaro.org
-
Neil Armstrong authored
Add an alias of LUCID OLE reset ops to EVO reset ops similar to other aliases. Signed-off-by:
-
Neil Armstrong authored
Document device tree bindings for display clock controller for Qualcomm SM8550 SoC. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
-
Bjorn Andersson authored
v6.2-rc1 + 1672656511-1931-1-git-send-email-quic_akhilpo@quicinc.com
-
Akhil P Oommen authored
Add support for the newly added 'synced_poweroff' genpd flag. This allows some clients (like adreno gpu driver) to request gdsc driver to ensure a votable gdsc (like gpucc cx gdsc) has collapsed at hardware. Signed-off-by:
Akhil P Oommen <quic_akhilpo@quicinc.com> Reviewed-by:
Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by:
-
Ulf Hansson authored
Some genpd providers doesn't ensure that it has turned off at hardware. This is fine until the consumer really requires during some special scenarios that the power domain collapse at hardware before it is turned ON again. An example is the reset sequence of Adreno GPU which requires that the 'gpucc cx gdsc' power domain should move to OFF state in hardware at least once before turning in ON again to clear the internal state. Signed-off-by:
-
Abel Vesa authored
By adding the newly added clk_sync_state_disable_unused as sync_state callback to all sdm845 clock providers, we make sure that no clock belonging to these providers gets disabled on clk_disable_unused, but rather they are disabled on sync_state, when it is safe, since all the consumers build as modules have had their chance of enabling their own clocks. Signed-off-by:
Abel Vesa <abel.vesa@linaro.org> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
-
Abel Vesa authored
There are unused clocks that need to remain untouched by clk_disable_unused, and most likely could be disabled later on sync_state. So provide a generic sync_state callback for the clock providers that register such clocks. Then, use the same mechanism as clk_disable_unused from that generic callback, but pass the device to make sure only the clocks belonging to the current clock provider get disabled, if unused. Also, during the default clk_disable_unused, if the driver that registered the clock has the generic clk_sync_state_disable_unused callback set for sync_state, skip disabling its clocks. Signed-off-by:
-
Bartosz Golaszewski authored
Extend the driver with a description of clocks for sa8775p platforms. Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by:
-
Bartosz Golaszewski authored
Add a new compatible for SA8775P platforms. Signed-off-by:
-
Yang Yingliang authored
It should be 'mux' passed to IS_ERR/PTR_ERR(). Fixes: 56a655e1 ("clk: qcom: krait-cc: convert to parent_data API") Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Signed-off-by:
-
- 06 Jan, 2023 4 commits
-
-
Abel Vesa authored
The TCSR clock controller found on SM8550 provides refclks for PCIE, USB and UFS. Add clock driver for it. This patch is based on initial code downstream. Signed-off-by:
-
Abel Vesa authored
Adds the RPMH clocks present in SM8550 SoC. Signed-off-by:
-
Abel Vesa authored
Add bindings and update documentation for clock rpmh driver on SM8550. Signed-off-by:
-
Abel Vesa authored
Add bindings documentation for clock TCSR driver on SM8550. Signed-off-by:
-
- 02 Jan, 2023 1 commit
-
-
Krzysztof Kozlowski authored
GCC clock controller is supplied by CX power domain: sc8280xp-crd.dtb: clock-controller@100000: Unevaluated properties are not allowed ('power-domains' was unexpected) Signed-off-by:
-
- 29 Dec, 2022 1 commit
-
-
Marijn Suijten authored
According to generic rules the SoC name should be first: arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dtb: clock-controller@5f00000: compatible: 'oneOf' conditional failed, one must be fixed: 'qcom,dispcc-sm6125' does not match '^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+-.*$' And this is already reflected by the bindings submitted prior to the addition of this driver. Any DTS following these rules will end up with a non-probing driver because of this mismatch. Fixes: 6e87c8f0 ("clk: qcom: Add display clock controller driver for SM6125") Signed-off-by:Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by:
-
- 28 Dec, 2022 22 commits
-
-
Konrad Dybcio authored
Add support for the camera clock controller found on SM6350. Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
-
Konrad Dybcio authored
Add device tree bindings for camera clock controller for Qualcomm Technology Inc's SM6350 SoC. Signed-off-by:
-
Dmitry Baryshkov authored
Now that all clocks have individual names, remove the names of SoCs from the SMD RPM clock definitions. Replace it with the common clk_smd_rpm_ prefix. Reviewed-by:
Alex Elder <elder@linaro.org> Reviewed-by:
-
Dmitry Baryshkov authored
Add special macro for the clocks of QCOM_SMD_RPM_BUS_CLK type. Use it to insert the _bus_N part into the clock symbol name. The system (and userspace) name of these clocks remains intact. Reviewed-by:
-
Dmitry Baryshkov authored
Rename the qcm2290_rf_clk3 clocks adding 38m4 prefix to distinguish it from the common (19.2 MHz) rf_clk3. The system (and userspace) name of these clocks remains intact. Reviewed-by:
-
Dmitry Baryshkov authored
To ease distinguishing between branch and non-branch clocks (e.g. aggre1_noc, aggre2_noc and qdss) add '_branch' to all SMD_RPM_BRANCH* clocks. The system (and userspace) name of these clocks remains intact. Reviewed-by:
-
Dmitry Baryshkov authored
Remove the duplication between the names of the normal and active-only clocks by moving common sufixes to the clock definition macros. This simplifies adding new clock definitions and reviewing existing defs. Reviewed-by:
-
Dmitry Baryshkov authored
Remove the duplication between the names of the normal and active-only XO_BUFFER and XO_BUFFER_PINCTRL clocks by using preprocessor logic to add _a suffix. Reviewed-by:
-
Dmitry Baryshkov authored
Rename msm8974_diff_a_clk, msm8974_div_a_clk1 and msm8974_div_a_clk2 to move the _a suffix to the end of the name. This follows the pattern used by other active-only clocks and thus makes it possible to simplify clock definitions. This changes the userspace-visible names for this clocks. Reviewed-by:
-
Dmitry Baryshkov authored
To ease review and reuse group all clock definitions together. Reviewed-by:
-
Dmitry Baryshkov authored
The commit 52a436e0 ("clk: qcom: smd-rpm: Switch to parent_data") introduced ragged right alignment for the line breaking backslash. Fix it to make the code look consistently. Reviewed-by:
-
Dmitry Baryshkov authored
The rpm_status_id field is a leftover from the non-SMD clocks. It is of no use for the SMD-RPM clock driver and is always equal to zero. Drop it completely. Reviewed-by:
-
Dmitry Baryshkov authored
For each XO_BUFFER_PINCTRL there is a corresponding XO_BUFFER clock. Add them automatically to drop the duplication between the clock definitions. Reviewed-by:
-
Dmitry Baryshkov authored
Reuse sm6125's MMAXI clocks for sm6375. Reviewed-by:
-
Dmitry Baryshkov authored
For each of XO_BUFFER_PINCTRL clocks there is a corresponding XO_BUFFER clock with the similar name (e.g. msm8998_ln_bb_clk3_pin vs msm8998_ln_bb_clk3). For qcs404_ln_bb_clk_pin there is no qcs404_ln_bb_clk, since the msm8992_ln_bb_clk was used instead (even for qcs404 platform). Follow the usual practice and rename msm8992_ln_bb_clk clocks to qcs404_ln_bb_clk (and rename active-only clock in a similar way). This is a preparation step for the next patch, which will merge XO_BUFFER and XO_BUFFER_PINCTRL definitions. Reviewed-by:
-
Dmitry Baryshkov authored
The qcm2290's ln_bb_clk2 is identical to the freshly added msm8998's ln_bb_clk2 one. Use the latter and drop the SoC-specific version. Reviewed-by:
-
Dmitry Baryshkov authored
Newer platforms (msm8998, sdm660, sm6125) have low noise LN_BB_CLKn clocks. The driver already uses proper clock indices (RPM_SMD_LN_BB_CLKn). Fix clock names used by these platforms. Fixes: a0384ecf ("clk: qcom: smd-rpm: De-duplicate identical entries") Fixes: edeb2ca7 ("clk: qcom: smd: Add support for SM6125 rpm clocks") Reviewed-by:
-
Dmitry Baryshkov authored
Reuse qcs404's QPIC and BIMC_GPU clock for qcm2290. Fixes: 78b727d0 ("clk: qcom: smd-rpm: Add QCM2290 RPM clock support") Reviewed-by:
-
Dmitry Baryshkov authored
The commit 644c4229 ("clk: qcom: smd: Add SM6375 clocks") added a duplicate of the existing define QCOM_SMD_RPM_MMAXI_CLK, drop it now. Fixes: 644c4229 ("clk: qcom: smd: Add SM6375 clocks") Reviewed-by:
-
Dmitry Baryshkov authored
The commit eaeee28d ("clk: qcom: smd: Add support for QCS404 rpm clocks") defined the pin-controlled ln_bb_clk clocks, but didn't add them to the qcs404_clks array. Add them to make these clocks usable to platform devices. Fixes: eaeee28d ("clk: qcom: smd: Add support for QCS404 rpm clocks") Reviewed-by: Alex Elder <elder@linaro.org? Reviewed-by:
-
Dmitry Baryshkov authored
Add pin-controlled Low-Noise BB clock definition. Signed-off-by:
-
Konrad Dybcio authored
Just like in case of other SoCs change SDCC1/SDCC2 ops to floor to avoid overclocking the controller. Fixes: cbe63bfd ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by:
Iskren Chernev <me@iskren.info> Signed-off-by:
-
- 27 Dec, 2022 1 commit
-
-
Dmitry Baryshkov authored
Add support for two GDSCs provided by this clock controller. Reviewed-by:
-
